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agilent parbert 81250 parallel bit error ratio tester product overview version 6.0 the only modular parallel bit error ratio test solution with ? different modules covering a range of data rates from 333 khz to 13.5 ghz ? up to 66 synchronous input and output channels ? powerful pattern sequencer providing looping and branching on events enabling control of complex tests and devices ? prbs/prws and memory based patterns up to 64mb ? delay control input for jitter generation ? error detector modules featuring individual cdr ? measurement suite
2 page 2/64 parbert 81250 main overview section page agilent parbert 81250 overview 3 fundamental parbert platform description 4 parbert 81250 key features 6 parbert 81250 measurement software 9 data editor and postprocessing tools 16 parbert 81250 application examples 17 agilent n4872a parbert 13.5 gb/s generator 24 agilent n4873a parbert 13.5 gb/s analyzer 24 agilent n4874a parbert 7 gb/s generator 31 agilent n4875a parbert 7 gb/s analyzer 31 agilent e4861b parbert 3.35 gb/s data module 38 agilent e4862b parbert 3.35 gb/s generator front-end 38 agilent e4863b parbert 3.35 gb/s analyzer front-end 38 agilent e4832a parbert 675 mb/s data module 44 agilent e4838a parbert 675 mb/s generator front-end 44 agilent e4835a parbert 675 mb/s analyzer front-end 44 agilent e4809a, e4808a and e4805b central clock modules 49 general characteristics 55 quick ordering guide - overview 58 product structure - parbert 81250 61 storage of customer specific data 63 related literature 63 table of contents
agilent parbert 81250 overview the parbert 81250 is the ? exible and scalable physical layer test solution that, based on its modular bert engine, enables characterization of high-speed multi-port devices in the computer, communications and feeding semiconductor industry. the modular parbert 81250 can be tailored to individual test needs with up to 132 1) synchronous channels . different modules are available for the parbert 81250 system that cover data generation and analysis from 333 kb/s up to 13.5 gb/s . once purchased in a certain con? guration parbert 81250 can easily be extended to ? t future needs protecting your investment. broad spectrum of applications originally designed to test and characterize synchronous devices such as a mux/demux typical for the communications industry parbert 81250 is equally suited for clock synchronous multi-port and multiple serial applications such as can be found in the computer industry . powerful pattern sequencer for uninterrupted testing running complex tests with a variety of test patterns in one shot without stopping the instrument for pattern download is enabled through the powerful parbert 81250 pattern sequencer with its up to ? ve nested loop levels and branching on external and internal events or upon sw command. in-depth insight into designs and devices the measurement suite automates the parameter variation of parberts ber- measurements to achieve and visualize insight into the duts parametric performance, e.g. producing eye diagrams, or doing timing margin analysis with ber-scan bathtub-plots with rj-dj jitter decomposition. jitter injection via the delay control input of the 13.5 / 7 / 3.35 gb/s data generator modules allows in depth receiver margining including jitter tolerance tests. application support parberts software package contains setup and processing tools for 10gbe and sonet/sdh. the n5990a test automation platform enables simple compliance test with parbert for different standards such as pci express?, mipi , display port (dp) and hdmi . application and product notes describing a variety of test applications with parbert are available for download from www.agilent.com/? nd/parbert . parbert 81250 key characteristics: ? modular bert platform for physical layer test and characterization ? modules of various speed classes up to 13.5 gb/s ? up to 66 synchronous generator and analyzer channels ? powerful pattern sequencer to control complex devices prbs/prws 2) and memory based patterns ? delay control input to apply external jitter sources 3) ? integrated clock data recovery to test clock-less interfaces 4) ? comprehensive measurement suite note: 1) 66 or 30 channels max with 3.35gb/s or 13.5gb/s modules 2) prws, pseudo random word sequence, is a special hardware generated pattern, based on prbs, to test mux/demux 3) 3.35 gb/s, 7gb/s and 13.5 gb/s generator modules only 4) 7 gb/s and 13.5 gb/s analyzer modules only parbert 81250 main overview page 3/64
parbert 81250 is designed as a ? exible data generator/ analyzer platform for physical layer test and characterization. it can be used for a large variety of applications and by this meets your individual needs. a module based system the parbert 81250 consists of the user sw and the parbert modules. these can be categorized by their maximum data rate (675mb/s, 3.35gb/s and 7/13.5gb/s) and their functionality (clock or data). a minimum system consists of one clock module and one data module forming a so-called clock group which is installed in the parbert vxi-mainframe. the mainframe can hold multiple clock groups; each is operated through its own graphical user interface (gui). three main speed classes the high-speed modules for 13.5 gb/s and 7 gb/s are dedicated generator or analyzer modules with one data channel each. the generators provide differential data and full rate clock output. they are equipped with an externally voltage controllable delay line to generate data streams with up to 200ps of peak-to-peak jitter. the analyzer modules feature an integrated clock data recovery cdr. the 3.35 gb/s data modules can carry up to two generator or analyzer front-ends of any combination. equivalent to the high speed modules the generator front-ends feature a voltage controlled delay for jitter generation but, according to the lower data rate, with a wider range of 500ps. the 675 mb/s data module back-ends can hold up to four generator or analyzer front ends and combinations thereof. a special capability of these back- end modules is the internal digital and analog channel- add function which e.g. allows generation of multi-level signals. up to 132 channels parbert 81250 uses the standard vxi mainframe with its 13 slots, where the leftmost slot is always reserved for the so- called slot-0 controller so that 12 slots are available for parbert- modules, i.e. clock and data. a maximum of three mainframes can be combined to form a clock synchronous system, which for the 675mb/s speed class and its 1-slot-wide clock module per frame yields up to 132 data channels (3 x 11 x 4). fundamental parbert platform description page 4/64 parbert 81250 main overview
table 1, a selection guide, lists the maximum number of channels per speed class together with some features or key speci? cations such as user memory depth or input / output voltage level ranges. multiple users at the same time the parbert 81250 hardware is controlled by the parbert user sw via an ieee 1394 ? rewire link. the sw is running on an external pc. it consists of three parts: a ? rmware server and two clients, the graphical user interface (gui) which allows instrument setup and basic (ber-) measurements and the measurement user interface (mui) which provides a variety of parametric physical layer measurements based on ber- measurements. gui and mui can either run on the pc which hosts the ? rmware server and controls the hw or on any other pc which is connected (e.g. via lan) to that pc mentioned above. they control measurements on any of the installed clock groups. each clock group can be controlled by a different user. plug&play drivers simplify controlling parbert 81250 through agilent vee, c/c++ or visual basic programs or by scpi based language via gpib. parbert 81250 main overview page 5/64 table 1. brief selection guide for parbert 81250 selection guide for parbert 81250 target data rate range 333.334 kb/s to 675 mb/s 20.834 mb/s to 3.35 gb/s 620 mb/s to 7 gb/s, 620 mb/s to 13.5 gb/s data module back-ends e4832a e4861a n/a n/a generator front ends e4838a e4862a n/a n/a analyzer front ends e4835a e4863a n/a n/a generator modules n/a n/a n4874a n4872a analyzer modules n/a n/a n4875a n4873a compatible clock modules e4805b/e4808a/ e4809a e4808a/e4809a e4809a e4809a max. number of channels 1 , 1 frame / 3 frames 44 / 132 22 / 66 10 / 30 10 / 30 adressed i/o technology lvds, pecl, ecl, ttl, 3.3v cmos lvds, cml, pecl, ecl, low voltage cmos lvds, cml, pecl, ecl, low voltage cmos lvds, cml, pecl, ecl, low voltage cmos data capability prws/prbs prws/prbs prws/prbs prws/prbs user memory 2 mb 16 mb 64 mb 64 mb input / output differential & single ended differential & single ended differential & single ended differential & single ended data format rz, r1, nrz, dnrz rz, r1, nrz, dnrz nrz, dnrz nrz, dnrz transition times 20%-80% 0.5-4.5ns, var (10-90%) <75ps <20ps <20ps amplitude resolution 0.1-3.5v, 10mv 0.05v-1.8v, 10mv 0.1 1.8v, 5mv 0.1 1.8v, 5mv window -2.2 to 4v -2 to 3.5v -2 to 3v -2 to 3v input voltage ranges 0 to 5v -2 to 3v -2 to 1v, -1 to 2v, 0 to 3v -2 to 3v, 2vpp -2 to 3v, 2vpp sensitivity 50mv typ., diff. <50mv <50mv <50mv sample delay resolution 2ps 1ps 100fs 100fs 1. parbert 81250 controlled via ieee 1394 link and external pc
6 key features parallel ber measurements up to 13.5 gb/s for characterization of parallel or multi-lane interfaces parbert 81250 can generate and analyze data clock-synchronously. however, generator skew and analyzer sample point timing can be programmed independently per channel as well as generator levels or analyzer thresholds. the ber is reported per lane and port (see figure 2). prbs/prws and user defined patterns a common test pattern for serial (communication) links is a pseudo random binary sequence prbs. to simplify mux/demux testing parbert provides the so-called pseudo-random-word sequences (prws) for generation and as expected data for analysis. a prws consists of a prbs per lane with a lane-to-lane delay chosen such that, when muxed together, the same prbs-polynomial as on each lane of the parallel side is generated on the serial side. the appropriate lane-to-lane delay is determined by the number of lanes (see figure 3). in addition, parberts pattern memory enables user defined test patterns as well. pattern sequencer physical layer testing includes the establishment or termination of a connection or the set-up of a dut into a specific test mode, e.g. a loop-back of received data. furthermore, specific device parameters often correlate with suitable test patterns. to perform such complex tests in one shot without interruption to download different test patterns, the parbert 81250 is equipped with a powerful pattern sequencer allowing up to five nested loops and branching on internal and external events or upon sw command. set-up is made easy through the powerful parbert 81250 graphical sequence editor, which also aids you maneuvering around hw restrictions when setting up user patterns not directly matching selected block lengths. debugging of the test sequence is supported e.g. by highlighting the currently executed block within the sequence (see figure 5). combining sequencing and precise timing with internal or external generator channel-add allows realization of e.g. user defined multi-level or de-emphasized signals. page 6/64 parbert 81250 main overview figure 2. ber results screen figure 3. mux/demux application: relationship between prbs and prws figure 5. parbert detail mode sequence editor screen figure 4. mechanism of auto-phase and auto-delay assignment
7 automatic data synchronization the latency between dut input and output is often not exactly known or not even deterministic. having to set parberts sample point for analysis manually would be tedious. therefore parbert 81250 analyzers provide three modes to automatically synchronize and align upon expected data with ber below a user defined threshold as a criteria (figure 5). ? auto bit sync finds the proper bit position in a data stream. for memory based patterns a unique detect word is required. automated phase alignment is optional. ? fast bit sync possible for prbs/prws only. especially useful for burst-mode applications, e.g. optical re-circulating loops. ? auto delay align only the sample point timing of the analyzers is adjusted. the latency between input and output must be within the delay range of the analyzers used. for applications w/o expected data with parbert running in data acquisition mode, e.g. for a/d test, proper sample point adjustment can automatically be achieved with the cdr / lane mode (7 and 13gb/s analyzer modules only) interrupt-free change of analyzer and generator delay the analyzer sample timing can be adjusted 1 period while the instrument keeps running w/o interrupting the measurement (see figure 7). for the 13.5 gb/s, 7 gb/s and 3.35 gb/s the delay of the genera- tor modules can be adjusted 1 period while running as well. figure 7. analyzer delay can be changed without stopping the system, cdr/lane can be enabled parbert 81250 main overview page 7/64 figure 6. parbert standard mode sequence editor with prbs/prws patterns and data synchronization mode chosen
different data rates the architecture of parbert 81250 allows using data modules of dif ferent speed classes in one clock group. choosing the right combination of system data rate and binary frequency multipliers (, 1/16, 1/8, 1/4, 1/2, 1 , 2 ,4 ,8 , 16, ) enables each module to operate within its valid data rate range. furthermore even channels within one module can operate at different data rates of binary ratio (see figure 8). parbert can be configured with one or more clock groups each controlled via an independent instance of the gui. the clock groups can either run completely independent from each other or can be locked to each other in a frequency ratio of m/n, with m, n=1256 and m x n<1024. in chapter "parbert 81250 application examples" on page 17 some configurations with two clock groups are shown. jitter injection and spread spectrum clocking ssc receiver margining is a measurement that is very demanding in terms of signal conditioning capabilities of the stimulating pattern generator, because it shall emulate worst case conditions as they may appear in mission mode of the dut or as they are specified in relevant standards. for this purpose not only voltage levels and cross point of differential signals shall be adjustable. jitter shall be injected as well. for this purpose the higher data rate modules of parbert, i.e. the 3.35 gb/s, 7gb/s and 13.5 gb/s generator modules are equipped with a delay control input, that allows phase modulation of the data output signals equivalent to the applied voltage signal. modern computer standards use spread spectrum clocking (ssc) techniques to decrease the power density of radiated emissions per frequency. the 13.5 ghz clock module allows direct feed-through of such a multi-ui low frequency modulated external clock enabling the data modules to generate and analyze such data patterns with ssc. agilent's signal generators can be used to generate such a modulated clock. figure 8. parameter editor for setting multiple frequencies in one system page 8/64 parbert 81250 main overview
parbert 81250 measurement software parbert measurement software consists of six different measurements that deliver graphical and numerical results allowing in- depth characterization for use in r&d and device verification (d v). fast pass/ fail tests a gainst user definable limits for manufacturing purposes are provided as well. parbert, as any other bert, physically can only do one measurement: it digitizes the input signal with respect to a predefined threshold voltage and, at a predefined portion of the bit width (the sample point ), compares this to its expected data and counts an error if it doesnt match the expected binary value. parbert measurement software automates the variation of these mentioned parameters (sample point timing and threshold voltage) and the repetition of this measurement for a number of subsequent bits and by this allows performing a variety of measurements: 1. ber measurement, targeting the error performance of a complete system under test 2. dut output level measurement 3. eye opening 4. dut output timing measurement 5. spectral decomposition of jitter allowing in depth pin- and port-wise characterization of the output performance of a transmitter (tx) under test as it is typically required in r&d or during dv . graphical representation(s) of the test result (e.g., pseudo color plot and contour plots) are available as well as a multitude of extracted or extrapolated numerical values. pass/fail criteria can be defined for every numerical result, simplifying a fast test against limits making it well suited for manufacturing as well. reduction of test time as it is usually desired in manufacturing is possible using the 6. fast eye mask measurement that requires a much smaller number of measured bits. each of the six measurements is an active-x component, which simplifies its integration into any test executive written with agilent vee pro, national instruments labview, excel, agilent testexec, c/c++, c# and microsoft ? visualbasic. the mui comprises a windows (2000, xp or vista) based gui that simplifies test set-up and execution. measurement results can be exported and printed. the measurement software is included in the standard parbert 81250 soft ware package. it works as a client to the parbert firmware server and can run on that pc that hosts the firmware server and is connected to the hw through the slot -0 controller, or on any other pc that is connected (e.g. via lan) to this mentioned pc. parbert 81250 main overview page 9/64
ber measurement during the bit error ratio (ber) measurement sample point timing and threshold voltage are kept constant, usually at the optimum values in the middle of the txs output eye. parbert performs its standard ber-measurement as described above. compared to the ber- measurement of the regular gui which reports the number of received bits and errors and their ratio, the ber, as actual and accumulated values (for last measurement timeframe and since start of measurement), the ber measurement of the mui delivers additional information and measurement control: errors for expected ones and zeroes are counted and reported separately. repetitive and single shot measurements can be set-up along with error counting, run- mode options and stop criteria such as logging, automatic resynchroniza tion or stop after a specified number of errors, bits or seconds. these features enable r&d usage for root cause failure analysis (e. g. ber log during a temp cycle), as well as manufacturing with minimum sample sizes and short measurement times. page 10/64 parbert 81250 main overview measurement parameters compared bits errors from expected 0s errors from expected 1s total errors parameters from last measurement period accumulated parameters measurement mode single or repetitive repetition rate is programmable in seconds (in this mode resynchronization can be enabled) pass/fail for actual and accumulated parameters log file logs all measured parameters table 2. ber measurement
11 output level measurement this measurement performs an automated sweep of the analyzer threshold voltage at constant, usually optimum, sample timing, while it continuously measures the ber. the result is displayed in an unusual but intuitive way, i.e. the threshold voltage (the input parameter) is plotted on the vertical axis and the ber (the result), on the horizontal axis (figure 12a). a histogram of ber versus threshold is derived (figure 12b) and is used to calculate mean value and standard deviation for one- and zero-levels. furthermore the q- factor can be derived from the tail fitting operations of the innermost (highest low-level and lowest high-level) gaussian distributions of the ber histograms (figure 12c). figure 12a. ber versus threshold figure 12b. ber histogram versus threshold figure 12c. q from ber versus threshold numerical measurement results high/low level mean level amplitude threshold margin high/low level standard deviation peak to peak noise signal/noise ratio (rms & peak-to-peak) q-factor q-factor optimum threshold q-factor residual ber pass/fail for all numerical results each one can be enabled individually graphical result displays ber versus threshold ber histogram versus threshold q-factor from ber versus threshold table 3. output level measurements parbert 81250 main overview page 11/64
12 page 12/64 parbert 81250 main overview eye opening during this measurement both sampling point timing and analyzer thresh old voltage are automatically swept, while ber is recorded and plotted either as a pseudo-color- or a contour-plot (see figure 9 a,b,c), giving the user intuitive and in-depth information of the pulse- or eye-performance of the rx under test. range and resolution for the measurement parameters and pass/fail values are user definable. figure 9a/b/c. view the ber for one terminal as a pseudo color plot or contour plot or equal ber at ber threshold numerical measurement results optimum sample point delay optimum threshold eye opening (volt)phase margin pass/fail for all parameters each parameter can be individually enabled graphical result displays pseudo color plot ber-contour two markers: voltage, delay, ber table 4: eye opening
13 fast eye mask the eye opening measurement as above reveals a lot of detailed information but can be time con- suming, especially when a fine resolution has been chosen, which maybe required and toler- able during the r&d phase, but probably not during manufactur- ing. for this purpose the fast eye mask measurement was devel- oped. from one up to 32 meas- urement points can de defined where the ber shall be meas- ured. a measurement point is defined as a pair of sample point timing and threshold voltage. both can be defined in absolute values or relative to the automat- ically determined eye opening / optimum sampling point and threshold. very often six measurement points are sufficient (see figure 11) to guarantee a certain pulse/eye performance. for reasonable ber values the whole measure- ment usually only takes a few seconds. measurement results provided: ? ber at pre-defined sample point and threshold voltage ? pass/fail results parbert 81250 main overview page 13/64 figure 10. the fast eye mask setup and results window figure 11. the fast eye mask setup and results window 90% 50% 10% threshold voltage 100% time (ui) actual sampling point C0.4 _0.16 +0.1 +0.4
14 dut output timing measurement probably the most important routine as it enables a real measurement of total jitter (tj ) in contradiction to just an extrapolation. in addition it performs jitter decomposition and delivers numerical results for random (rj) and deterministic jitter (dj) according to the dual-dirac model. during this measurement the sample point timing is automati- cally swept with constant, usually optimum analyzer threshold volt- age while ber is continuously measured. the result display of this so-called ber-scan measurement, i.e. the ber vs the sample point delay, is because of its shape, often called the bath tub curve. all measured curves are centered around the optimum sampling point delay of the port allowing to determine edge to edge skew between the data lanes of a data port. clock to data delay per channel equivalent to set-up and hold-time condition of a rx driven by the tx under test, can be measured. when (depending on the synch mode) absolute timing is available , the delay value at optimum sample point is provided as well. there is also a numerical view that shows the numerical return values for the selected ber threshold only. another flavor of the ber-scan is the fast total jitter (ftj) meas- urement, which by measuring for each delay point only as many bits as required to determine if the ber is above or below the target ber, delivers the horizontal eye opening, i.e. the tj in much shorter time. figure 10a. view the dut output measurement results as a bathtub curve figure 10b. view the dut output measurement results as a histogram page 14/64 parbert 81250 main overview timing parameters optimum sample point delay phase margin clock to data out minimum clock to data out maximum skew between channels jitter parameters rms jitter mean value peak peak jitter for speci? c ber pass/fail for all timing and jitter parameters each parameter can be individually enabled graph view of ber versus sample delay 2 markers: delay, ber table 6. dut output timing measurement
15 parbert 81250 main overview page 15/64 spectral jitter decomposition this measurement is dierent rom all the aboe beause the sample point is unusually set eatly to the rossin point o the eye and beause it is post proessin the aptured error data utiliin t to etrat the desired result ie the embedded itter spetrum this is etremely helpul or to separate deterministi omponents rom the andom itter noise loor and by this pinpointin e soures o undesired r osstal sin this measurement with passail limits applied durin manuaturin t est it ensures that ertain nown ontributory itter reuenies do not inrease aboe a sae limit ou an also measure the reueny response o a or a s in one shot by applyin white random itter on the re lo or the inomin data stream see iure b figure 11b. jitter transfer of a cdr with a corner frequency of approximately 40 mhz figure 11a. spectral decomposition of jitter with a large peak at 1mhz measurement parameters data segment length fft windowing numerical results ber, total power, noise power, frequency and power of n highest power jitter frequencies pass/fail power factor graphical result displays spectrum graph (power vs. frequency) table 7. spectral decomposition of jitter
16 figure12a. 10 gbe processing tool figure 12b. sonet/sdh editor figure 12c. sf15 post processing data editor and postprocessing tools 10gb ethernet frame generator and post processing tool for 10gbe applications sonet/sdh frame generator for sonet/ sdh for serial (e.g. oc192, segment width = 1) or parallel applications (e.g. oc768, segment width = 4, or 16 depending on serializer (mux) in use) sfi5 post processing tool for analysis of 16 data lanes and 17th deskew (dsc) bit, which ensures that ? the 16 data channels are valid (valid prbs 2 7 - 1 or 2 11 - 1 ) streams ? the 16 data channels are within skew specification ? the dsc (17th) bit is valid - correct header - match to the 16 data channels page 16/64 parbert 81250 main overview
17 parbert 81250 main overview page 17/64 parbert is a very versatile instrument usable in a variety of different applications across the industries. some examples are briefly introduced below. in the context of this brochure the description is focused more on relevant parbert capabilities utilized for that specific applica- tion than on imparting in-depth knowledge on how to perform the related measurement task. for this purpose please refer to the related application notes which along with some other applications not mentioned here can be found under www.agilent.com/find/parbert. oc 192 probably the most basic and instructive application for parberts capabilities is a clock synchronous mux/de-mux test e.g. found in the sonet/ oc 192 telecom arena. parbert masters the requirements resulting from the different data-rates at the parallel and serial side easily and cost efficient utilizing modules of different speed classes and running them at (binary weighted) data rates as depicted in figure 8. parbert 81250 application examples for the different tests parbert can be connected at either inter- face for signal generation and/or analysis so that both parts (mux and de-mux) can be tested simul- taneously creating an environ- ment similar to mission mode of the dut and furthermore saving test time. depending on the desired test result and the test patterns used it can however be advantageous to use more than one central clock module and combine generators and analyzers in sepa- rate clock groups eliminating limitations in synchronization. figure 13. oc 192 example
10gbe-xaui this example depicted in figure 14, seems similar to the one above as the dut again is some sort of mux/demux. however, in this 10gbe lan application the data rates between parallel (xaui: 4 x 3.125 gb/s) and serial side 10gbe: 1 x 10.3125gb/s) have a ratio of 3.3 (= 4 x 8/10 x 66/64), which stems from the different codings on each side (8b/10b and 66b/64b). parbert can eit her be used as the clock master with e.g. one clock module running at 10.3125gb/s and the other at a rate of 10/33 or with both clock modules tied to the dut-internal reference clock multiplying this by 66 or 20 respectively. when the dut is a complete xenpac module with its electri- cal xaui-i/os on the parallel side and optical i/os on the serial side parbert can be complemented w/ optical e/o and o/e converter modules to completely address this application. again, it maybe advantageous to separate genera- tors and analyzers in different clock groups so that the optimum parbert configuration may con- sist of four clock modules and 6 data modules (2 x 13.5gb/s and 4 x 3.35gb/s with two generator or analyzer channels each). page 18/64 parbert 81250 main overview figure 14. 10 gbe xaui module
19 parbert 81250 main overview page 19/64 pon the last example from the optical communication domain is about passive optical networks (pon) based on time division multiple access (tdma) as used by gpon and bpon. the most critical sub-module in this system is the receiver rx of the optical line terminal (olt) in the central office which has to deal with the upstream signal bursts arriving from the optical network units (onu) as depicted in figure 15. the spacing between them is very short and the ampli- tude maybe very different, such that the rx in the olt must set- tle to the appropriate threshold and synchronize its internal pll in a very short time. a test set-up consisting of parbert 81250, agilents lightwave measurement system (lms) 8163b/8164b and a digital communication analyzer (dca) 81600c emulating the important portions of a pon is depicted in figure 16. parberts exact timing capability for the two data burst and the related laser control signals is essential for standard compliant testing and characteri- zation of the olts rx. the pattern sequencer allows the set-up and generation of the burst-packages with desired content. the sw controlling parbert and the other instruments can be written in a language of your choice. it can run on the same pc that the parbert sw resides on. using e.g. visual basic or c allows utilization of the plug & play libraries provided with parbert (and many other instruments), which simplifies programming a lot. for more information: www.agilent.com/find/pon subscriber onu central of?ce olt downstream broadcast long short guard time upstream tdma passive coupler e/o e/o e/o e/o o/e figure 15. tdma bursts travelling upstream on a passive optical network figure 41: tdma bursts travelling upstream on a passive optical network parbert awg jitter osa optical attenuator/power dca-j control 1 control 2 rx tx rx rx tx tx onu1 optical coupler olt (co) onu2 att1 att2 figure 16. parbert based test set-up for characterization of olt
hdmi the high-definition multimedia interface (hdmi) is an industry- supported, uncompressed, all- digital audio/video interface. hdmi provides a connection between any compatible digital audio/video source, such as a set-top box, dvd player, or a/v receiver and a compatible digital audio and/or video monitor, such as a digital television (dtv). for this application agilent provides a complete test solution, i.e. the agilent tmds signal generator. its hardware is based on parbert and the test sw is based on the n5990a test automation software platform. parbert provides the data channels d0, d1 and d2 to cover the three colors green, red and blue. the fourth channel d- is used as intra-pair skew channel to provide additional skew testing capability between normal and complementary data as defined in the hdmi standard. a clock signal is also provided. the sw guides the user through the test set-up (figure 17), allows the definition of parbert data packets in user terms with its hdmi frame generator and performs automated measure- ment of the full hdmi jitter tolerance curve. for more information: www.agilent.com/find/hdmi_ sink_test page 20/64 parbert 81250 main overview figure 1. sink test connection setup example lan firewire bias-ts dc power supply +3.0 v 10 mhz out clock in data clock in clock 10 mhz in patt trig in event 1 dc power supply +5 v sink dut
mipi the mobile industry processor interface (mipi) is a standard used throughout the field of mobile communication. several versions addressing different speed classes are already defined or under definition. mipi d-phy is the standard for a serial bus used in battery operated equipment (e.g. a cell phone) to connect high data capacity devices like the camera module. battery life is always a key issue of portable electronics. mipi d-phy therefore operates in two modes, low power/low data rate (max 20 mbit), and high data rate mode. the low power mode works single ended on standard cmos levels while signaling and high data rate use lvds. the transition between modes happens dynami- cally and is therefore one of the critical areas that require testing. using parbert modules of dif- ferent speed classes and adding their output signals passively allows generation of the depicted waveform (figure 18) with the parbert-typical freedom to define all levels timing and data content enabling tailored receiver stress tests for r&d and manufacturing. for more information: www.agilent.com/find/mipi_ dphy figure 18. oom into the bit level of the d-ph stimulus signal switching between hs and p mode parbert 81250 main overview page 21/64
page 22/64 parbert 81250 main overview pci express pcie shall be used as an application example from the computer industry. this bus consists of up to 16 differential point to point connections, so called lanes. architectural it is not a traditional synchronous, parallel bus instead a multiple serial bus. symbol rates are 2.5gb/s, 5gb/s and 8gb/s for the three generations of the standard already defined or in process. generation 1 and 2 use 8b/10b coding with a relatively high overhead of 25%. for the third generation this coding scheme was dropped because of its data rate penalty. for the first generation with its moderate symbol rate of 2.5gb/s an rx t est was not defined. this has changed since the second generation, where for rx jitter tolerance test, a quite complicated cocktail was defined. w hile a single lane can be tested with a serial bert such as the agilent n4903 j-bert, an extensive and more realistic simultaneous test of more than one lane can only be achieved with a parbert. in order to generate test patterns with the required jitter cocktail parbert makes use of its jitter modulation capability via the external delay control input. figure 19 shows a setup with agilent 33220 and 81150a acting as jitter modulation s ources. the whole setup is structured into three clock groups. the first with the 33250 being connected only generates a modulated clock that the second parbert system runs from. with the help of the 81150a and an accessory filter the random jitter rj with the required spectral distribution is created. the third clock group holds parbert analyzers that by measuring ber check if the rx under test tolerated the amount of jitter applied at its input and extracted the data content correctly, i.e. with a ber below the specified limit. parbert frame #1 parbert frame #2 clk out clk out clk in clk in data out data out data in data in delay ctrl in delay ctrl in clk out data out delay ctrl in clk out data out delay ctrl in clk out data out delay ctrl in clk out data out delay ctrl in n4872a n4874a n4809a reference clock group 33220a 100 mhz ref clk from dut = 5 ghz clock signal + 75 ghz ssc residual = 2.5 ghz clock signal = 11636b power divider analyzer clock group generator clock group n4809a n4809a 33220a 81150a isi board rj filter board to dut n4875a n4875a n4875a n4875a n4874a n4874a n4874a n4875a figure 19. example measurement set-up for a pcie rx test with 4 data lanes specified test patterns can be created utilizing parberts custom pattern memory and its sequencer. external control sw takes care of proper calibration and test automation. for more information: www.agilent.com/find/pcie receivertest
a/d converter test this last example, basically a semiconductor test application, is very interesting in such that a parallel bit error tester, i.e. the parbert is used although literally a ber cannot be measured at all. the dut is an a/d converter such as it is used in satellite commu- nications. the problem that an a/d converter as a dut presents to a bert lies in the nature of a/ d conversion. even if the a/d converter works within its speci- fication, quantization may have an inaccuracy of at least a bit, probably a few. this means, that when applying an analog input signal at the a/ds input, its out- put value can not be p redicted bit-wise. so the only way of test- ing the performance of the a/d converter is capturing its output data, and doing an appropriate post processing on the uploaded data. the analog input signal for the a/ d test may come from a signal generator or, in a back-to-back configuration, from an appropri- ate d/a converter driven by parbert generators. analyzers with their deep capture memory are used to record the a/ds output data and make it available for later post processing. although this set-up sounds sim- ple, details such as setting a cor- rect sample delay maybe tricky, as the overall propagation delay of the a/d converter or an indi- vidual lane maybe unknown. all the nice bert-typical autosyn- chronization features that parbert offers do not work, as they need expected data. however, parbert solves this problem in a very user friendly way: its built-in cdr with its cdr/channel feature enables automated sampling at optimum sample point for each channel. parbert analog signal input differential digital data outputs signal generator dut: a/d converter e4809a central clock e4873a or e4875a analyzer modules figure 20. example measurement set-up for an 8bit a/d converter utilizing parbert's cdr/ channel feature for automated optimization of sampling point parbert 81250 main overview page 23/64
24 page 24/64 parbert 81250 main overview agilent parbert 81250 data modules and front-ends agilent n4872a parbert 13.5 gb/s generator agilent n4873a parbert 13.5 gb/s analyzer technical specifications version 1.0 general the n4872a generator and n4873a analyzer modules are each one vxi slot wide and oper- ate in a range from 620 mb/s up to 13.5 gb/s. the parbert 13.5 gb/s modules require the e4809a 13.5 ghz central clock module, which is two vxi slots wide. all specifications, if not otherwise stated, are valid at the end of the recommended n4910a cable set (24'' matched pair 2.4 mm). the n4872a generator module generates hardware-based prbs up to 2 31 - 1, prws and user- defined patterns and provides a memory depth of 64 mbit. the n4873a can synchronize on a 48 bit detect word, or on a pure prbs pattern without detect word. timing specifications the parbert 13.5 gb/s modules are able to work with three dif- ferent clock modes. ? internal clock mode: the common clock mode is provided by the e4809a 13.5 ghz central clock module, which generates clock frequencies up to 13.5 ghz. figure 21. n4872a & n4873a and waveform frequency range 620 mb/s to 13.5 gb/s delay = start delay + fine delay can be specified as leading edge delay in fraction of bits in each channel start delay range 0 to 100 ns fine delay range 1 period (can be changed without stopping) delay resolution 100 fs delay accuracy 10 ps 20 ppm relative to the zero-delay placement. (@ 25 c - 40 c ambient temp.) relative delay accuracy 2 ps 2% typ. (@ 25 c - 40 c ambient temp.) skew between modules of same type 20 ps after cable deskewing at customer levels and unchanged system frequency. (@ 25 c - 40 c ambient temp.) ? external clock mode: the system also works synchro- nously with an external clock, which is connected to the e4809a clock module. ? cdr mode: to use the n4873a 13.5 gb/s analyzer cdr capabilities, connect the analyzers cdr out to the e4809a clock modules clock in. table 10. n4872a data generator timing specifications (@ 50% of amplitude, 50 to gnd)
25 parbert 81250 main overview page 25/64 sequencing the sequencer receives instruc- tions from the central sequencer and generates a sequence. the channel sequencer can generate a sequence with up to 60 segments. an analyzer channel generates feedback signals that can control the channel sequencer and/or the central sequencer. with parallel analyzer channels, the feedback is routed to the cen- tral sequencer to allow a com- mon response of all parallel channels. with a single receive channel, the channel sequencer itself handles the feedback signals. pattern generation the data stream is composed of segments. a segment can be made up of a memory-based pat- tern, memory-based prbs or hardware generated prbs. a total of 64 mbit (at segment length resolution 512 bits) are available for memory-based pat- tern and prbs. memory-based prbs is limited to 2 15 - 1 or shorter. memory-based prbs allows special prbs modes like zero substitution (also known as extended zero run) and variable mark ratio a zero substitution pattern extends the longest zero series by a user selectable number of addi- tional zeroes. the next bit follow- ing these zero series will be forced to 1. mark ratio is the ratio of 1 s and 0 s in a prbs stream, which is 1/2 in a normal prbs. variable mark ratio allows values of 1/8, 1/4, 1/2, 3/4 and 7/8. due to granularity reasons a prbs has to be written to ram several times, at a multiplexing factor of 512 the number of repe- titions is also 512. that means that a 2 15 - 1 prbs uses up to 16 mbit of the memory. hardware- based prbs can be a polynomial up to 2 31 - 1. no memory is used for hardware-based pattern gen- eration. error insertion allows inserting single or multiple errors into a data stream. so instead of a 0 a 1 is generated and vice versa. table 12. data rate range, segment length resolution, available memory for synchronization and fine delay operation table 11. n4872a pattern and sequencing data rate range, mb/s segment length resolution maximum memory depth, bits 620 1.350,000 32 bits 4,194,304 620 2.700,000 64 bits 8,388,608 620 5.400,000 128 bits 16,777,216 620 10.800,000 256 bits 33,554,432 620 13.500,000 512 bits 67,108,864 patterns: memory based up to 64 mbit prbs/prws 2 n - 1, n = 7, 10, 11, 15, 23, 31 mark density 1/8, 1/4, 1/2, 3/4, 7/8 at 2 n - 1, n = 7, 9, 10, 11, 15 errored prbs/prws 2 n - 1, n = 7, 9, 10, 11, 15 extended ones or zeros 2 n - 1, n = 7, 9, 10, 11, 15 prws port width 1, 2 , 4, 8, 16
page 26/64 parbert 81250 main overview n4872a generator module the n4872a generates differen- tial or single-ended data and clock signals operating from 620 mb/s up to 13.5 gb/s. the output levels are able to drive high-speed devices with interfaces like lvds, ecl, pecl, cml and low voltage cmos. the nominal output impedance is 50 typical. the delay control in has a single- ended input with 50 impedance. the input voltage allows modula- tion of a delay element up to 1 ghz (200 ps) within t he generator's differential output. the aux in has a single-ended input with a 50 impedance. the aux in allows injecting gating signals. an active (ttl high) signal at the auxiliary input forces (gates) the data to a logic zero. data output 1, differential or single ended, 2.4 mm(f) (1) range of operation 620 mb/s - 13.5 gb/s impedance 50 typ. output amplitude/resolution 0.1 vpp C 1.8 vpp / 5 mv output voltage window C2.00 to +3.00 v short circuit current 72 ma max. external termination voltage C2 v to +3 v (2) data formats data: nrz, dnrz addressable technologies lvds, cml pecl; ecl (terminated to 1.3 v/0 v/-2 v) low voltage cmos transition times (20% - 80%) < 20 ps (3) jitter 9 ps peak-peak typ. (4) cross-point adjustment (duty cycle distortion) 20%80% typ. (1) in single-ended mode, the unused output must be terminated with 50 to gnd. (2) for positive termination voltage or termination to gnd, external termination voltage must be less than 3 v below voh. for negative termination voltage, external termination voltage must be less than 2 v below voh. external termination voltage must be less than 3 v above vol. (3) at ecl levels (4) clock out to data out clock output 1, differential or single-ended, 2.4 mm(f) (1) frequency 620 mhz - 13.5 ghz impedance 50 typ. output amplitude/resolution 0.1 vpp C 1.8 vpp / 5 mv output voltage window C2.00 to +2.80 v short circuit current 72 ma max. external termination voltage C2 v to +3 v (2) addressable technologies lvds, cml pecl; ecl (terminated to 1.3 v/0 v/-2 v) low voltage cmos transition times (10% - 90%) < 25 ps (3) jitter 1 ps rms typ. ssb phase noise (10 ghz @ 10 khz offset, 1 hz bandwidth) < C75dbc with clock module e4809a typ. (1) in single-ended mode, the unused output must be terminated with 50 to gnd. (2) for positive termination voltage or termination to gnd, external termination voltage must be less than 3 v below voh. for negative termination voltage, external termination voltage must be less than 2 v below voh. external termination voltage must be less than 3 v above vol. (3) at ecl levels data out clock out table 17. parameters for n4872a parbert 13.5 gb/s generator table 18. parameters for n4872a parbert 13.5 gb/s generator
27 parbert 81250 main overview page 27/64 delay control input single-ended; dc-coupled; sma(f) input voltage window C250 mv ... +250 mv (dc-coupled) input impedance 50 typ. data rate delay range modulation bandwidth C100 ps +100 ps dc 1 ghz @ < 10.5 gb/s delay control in interface dc coupled, 50 nominal levels ttl levels minimum pulse width 100 ns connector sma female aux in table 19. parameters for n4872a parbert 13.5 gb/s generator table 20. parameters for n4872a parbert 13.5 gb/s generator
n4873a analyzer module the analyzer features are: ? acquire data from start ? compare and acquire data around error ? compare and count erroneous ones and zeros to calculate the bit error rate receive memory for acquired data is up to 64 mbit deep, depending on segment length resolution. the stimulus portion of the channel generates expected data and mask data. mask data is also available at the maximum segment resolution (32, 64, 128, 256, 512). the analyzer is able to synchro- nize on a received data stream by means of a user selectable syn- chronization word. the sync. word has a length of 48 bits and is com- posed of zeros, ones and xs (don't cares). the detect word must be unique within the data stream. synchronization on a pure prbs data-stream is done without a detect-word, instead by simply loading a number of the incoming bits into the internal prbs gener- ator. a pre-condition for this is that the polynomial of the received prbs is known. the input comparator has differential inputs with 50 impedance. the sensitivity of 50 mv and the common mode range of the comparator allow the testing of all common differential high-speed devices. the user has the choice of using the differential input with or without a termina- tion voltage or as single-ended input (with a termination voltage). the differential mode does not need a threshold voltage, whereas the single-ended mode does. but also in differential mode the user can select one of the two inputs and compare the signal to a threshold voltage. sampling rate 620 mhz to 13.5 ghz sample delay can be specified as leading edge delay in fraction of bits in each channel start delay range 0 to 100 ns fine delay range 1 period (can be changed without stopping) delay resolution 100 fs delay accuracy 10 ps 20 ppm relative to the zero-delay placement (1) relative delay accuracy 2 ps 2% typ. (1) skew between modules of same type 20 ps after cable deskewing at customer levels and unchanged system frequency. (1) number of channels 1, differential or single ended, 2.4 mm (f) range of operation 620 mb/s - 13.5 gb/s max input amplitude 2 vpp input sensitivity 50 mvpp typical @ 10 gb/s, prbs 2 31 - 1, and ber 10 -12 input voltage range C2v +3 (selectable 2v window) internal termination voltage (can be switched off ) -2.0 to +3.0 v (must be within selected 2 v window) threshold voltage range C2.0 to + 3.0 v (must be within selected 2 v window) threshold resolution 1 mv minimum detectable pulse width 25 ps typ. phase margin (source: n4872a) 1 ui - 12 ps typ. impedance 50 typ. (100 differential, if termina- tion voltage is switched off) analyzer auto-synchronization on prbs or memory-based data manual or automatic by: bit synchronization(2) with or without automatic phase alignment automatic delay alignment around a start sample delay (range: 10 ns) ber threshold: 10 -4 to 10 -9 (2) with prbs data, analyzers can autosyncronize on incoming prbs data bits. when using memory-based data, this data must contain a unique 48 bit detect word at the beginning of the segment, and the generators must be on a separate system clock. dont cares within detect word are possible. if several inputs synchronize, the delay diffference between terminals must be smaller than 5 segment length resolution. page 28/64 parbert 81250 main overview table 21. n4875a analyzer timing: all timing parameters are measured at ecl levels, terminated with 50 to gnd table 22. n4873a pattern and sequencing table 23. parameters for n4873a parbert 13.5 gb/s analyzer (1) 25 c - 40 c ambient temperature
parbert 81250 main overview page 29/64 clock data recovery the analyzer module has integrated cdr capabilities, which allow the recovery of either clock or data. before the cdr can lock onto the incoming data stream, the data rate must be defined within the user interface; common data rates are pre-defined. in cdr mode, phase alignment to the center of the eye is done aut omatically during synchronization. for cor- rect operation, the cdr output must be connected to the clock input of the e4809a central clock module. in addition the generator clock source and the analyzer clock source must be independent. aux out the aux out provides data or recovered clock signals. aux in gating functionality: if a high level is applied at aux in, comparison is disabled and internal counters are stopped. after resuming a low level at aux in, comparison is enabled and internal counters continue. the internal sequencing is not stopped. error out whenever one or more bit errors are detected, the error out signal is high for one segment resolution. a high period is always followed by a low period (rz-format) in order to ensure trigger possibility on continuous errors. common data rates oc-192: 9.953 gb/s 10gbe: 10.3125 gb/s fiber channel: 10.51875 gb/s g.709/g.975: 10.664 gb/s/10.709 gb/s s-ata: 1.5/3.0/6.0 gb/s pci-express: 2.5/5.0/8.0 gb/ss oc-48: 2.488 gbit/s 10gbe (xaui): 3.125 gbit/s san: 3.187 gbit/s frequency ranges 9.9 ghz 10.90 ghz 4.23 ghz ... 6.4 ghz 2.115 ghz 3.2 ghz 1.058 ghz....1.6 ghz (1) the cdr works with speci? ed prbs patterns up to 2 31 - 1, the cdr expects a dc balanced pattern, the cdr expects an average transition density of one transition for every second bit. interface ac coupled, 50 nominal amplitude 600 mv nominal output jitter (clock @ aux out) 0.01 ui rms typical connector sma female (1) available for hardware s/n de43a00401 and software rev. 5.62 and above table 24. parameters for n4873a parbert 13.5 gb/s analyzer - clock data recovery table 25. parameters for n4873a 13.5 gb/s analyzer - aux out
technical specifications all specifications describe the instruments warranted perform- ance. non-warranted values are described as typical. all specifi- cations are valid from 10 to 40 c ambient temperature after a 30 minute warm-up phase, with outputs and inputs terminated with 50 to ground at ecl levels if not specified otherwise. resolution segment resolution ttl compatible internal 500 termination to gnd; threshold @ 1.5 v connector sma female low (0...1 v) internal counters are enabled high (2 v...4 v) internal counters are stopped open same as low format rz; active high output high level 0 v 100 mv output low level +1 v 100 mv connector sma female table 26. parameters for n4873a 13.5 gb/s analyzer - aux in table 27. parameters for n4873a 13.5 gb/s analyzer - error out page 30/64 parbert 81250 main overview
table 28. n4874a data generator timing specifications (@ 50% of amplitude, 50 ? to gnd) parbert 81250 main overview page 31/64 agilent n4874a parbert 7 gb/s generator agilent n4875a parbert 7 gb/s analyzer technical specifications general the n4874a generator and n4875a analyzer modules are each one vxi slot wide and oper- ate in a range from 620 mb/s up to 7 gb/s. the parbert 7 gb/s modules require the e4809a 13.5 ghz central clock module. all specifications, if not otherwise stated, are valid at the end of the recommended n4910a cable set (24'' matched pair 2.4 mm). the n4874a generator module generates hardware-based prbs up to 2 31 - 1, prws and user- defined patterns and provides a memory depth of 64 mbit. the n4875a can synchronize on a 48bit detect word, or on a pure prbs pattern without detect word. timing specifications the parbert 13.5 gb/s modules are able to work with three different clock modes. ? internal clock mode: the common clock mode is provided by the e4809a 13.5 ghz central clock module, which generat es clock frequencies up to 13.5 ghz. ? external clock mode: the system also works synchronously with an external clock, which is connected to the e4809a clock module. ? cdr mode: to use the n4875a 7 gb/s analyzer cdr capabilities, connect the analyzers cdr out to the e4809a clock modules clock in. figure 22. n4874a & n4875a and waveform frequency range 620 mhz to 7 ghz delay = start delay + fine delay can be specified as leading edge delay in fraction of bits in each channel start delay range 0 to 100 ns fine delay range 1 period (can be changed without stopping) delay resolution 100 fs delay accuracy 10 ps 20 ppm relative to the zero-delay placement. (@ 25 c - 40 c ambient temp.) relative delay accuracy 2 ps 2% typ. (@ 25 c - 40 c ambient temp.) skew between modules of same type 20 ps after cable deskewing at customer levels and unchanged system frequency. (@ 25 c - 40 c ambient temp.)
page 32/64 parbert 81250 main overview table 29. n4874a pattern and sequencing table 30. data rate range, segment length resolution, available memory for synchronization and fine delay operation sequencing the sequencer receives instructions from the central sequencer and generates a sequence. the chan- nel sequencer can generate a sequence with up to 60 segments. an analyzer channel generates feedback signals that can control the channel sequencer and/or the central sequencer. with parallel analyzer channels, the feedback is routed to the central sequencer to allow a common response of all parallel channels. with single receive channel, the channel sequencer itself handles the feedback signals. pattern generation the data stream is composed of segments. a segment can be made up of a memory-based pattern, memory-based prbs or hardware generated prbs. a total of 64 mbit (at segment length resolution 512 bits) are available for memory- based pattern and prbs. memory-based prbs is limited to 2 15 - 1 or shorter. memory-based prbs allows special prbs modes like zero substitution (also known as extended zero run) and variable mark ratio. a zero substitution pattern extends the longest zero series by a user selectable number of addi- tional zeroes. the next bit follow- ing these zero series will be forced to 1. mark ratio is the ratio of 1 s and 0 s in a prbs stream, which is 1/2 in a normal prbs. variable mark ratio allows values of 1/8, 1/4, 1/2, 3/4 and 7/8. due to granularity reasons a prbs has to be written to ram several times, at a multiplexing factor of 512 the number of repe- titions is also 512. that means that a 2 15 - 1 prbs uses up to 16 mbit of the memory. hardware-based prbs can be a polynomial up to 2 31 - 1. no memory is used for hardware-based pattern genera- tion. error insertion allows inserting single or multiple errors into a data stream. so instead of a 0 a 1 is generated and vice versa. data rate range (mbit/s) segment length resolution maximum memory depth (bits) 620 1.350,000 32 bits 4,194,304 620 2.700,000 64 bits 8,388,608 620 5.400,000 128 bits 16,777.216 620 7.000,000 256 bits 33,554.432 620 7.000,000 512 bits 67,108.864 segment length resolution 512 bit patterns: memory based up to 64 mbit prbs/prws 2 n - 1, n = 7, 9, 10, 11, 15, 23, 31 mark density 1/8, 1/4, 1/2, 3/4, 7/8 at 2 n - 1, n = 7, 9, 10, 11, 15 errored prbs/prws 2 n - 1, n = 7, 9, 10, 11, 15 extended ones or zeros 2 n - 1, n = 7, 9, 10, 11, 15 clock patterns divide or multiply by 1, 2, 4 prws port width 1, 2 , 4, 8, 16
parbert 81250 main overview page 33/64 table 32. parameters for n4874a parbert 7 gb/s generator table 31. parameters for n4874a parbert 7 gb/s generator n4874a generator module the n4874a generates differential or single-ended data and clock signals operating from 620 mb/s up to 7 gb/s. the output levels are able to drive high-speed devices with interfaces like lvds, ecl, pecl, cml and low voltage cmos. the nominal output impedance is 50 typical. the delay control in has a single-ended input with 50 impedance. the input voltage allows modulation of a delay element up to 1 ghz (200 ps) within the generator's differential output. the aux in has a single-ended input with a 50 impedance. the aux in allows injecting gating signals. an active (ttl high) sig- nal at the auxiliary input forces (gates) the data to a logic zero. data output 1, differential or single ended, 2.4 mm(f) (1) range of operation 620 mb/s - 7 gb/s impedance 50 typ. output amplitude/resolution 0.1 vpp C 1.8 vpp / 5 mv output voltage window C2.00 to +3.00 v short circuit current 72 ma max. external termination voltage C2 v to +3 v (2) data formats data: nrz, dnrz addressable technologies lvds, cml pecl - 3.3 v; ecl (terminated to 1.3 v/0 v/-2 v) low voltage cmos, lvds, cml transition times (20% - 80%) < 20 ps (3) jitter 9 ps peak-peak typ. (4) cross-point adjustment 20%80% typ. (1) in single-ended mode, the unused output must be terminated with 50 to gnd. (2) for positive termination voltage or termination to gnd, external termination voltage must be less than 3 v below voh. for negative termination voltage, external termination voltage must be less than 2 v below voh. external termination voltage must be less than 3 v above vol. (3) at ecl levels. (4) clock out to data out. clock output 1, differential or single-ended, 2.4 mm(f) (5) frequency 620 mhz - 7 ghz impedance 50 typ. output amplitude/resolu- tion 0.1 vpp C 1.8 vpp / 5 mv output voltage window -2.00 to +2.80 v short circuit current 72 ma max. external termination voltage C2 v to +3 v (6) addressable technologies lvds, cml pecl; ecl (terminated to 1.3v/0 v/-2 v) low voltage cmos transition times (10% - 90%) < 25 ps (7) jitter 1 ps rms typ. ssb phase noise (10 ghz @ 10 khz offset, 1 hz bandwidth) < - 75 dbc with clock module e4809a typ. (5) in single-ended mode, the unused output must be terminated with 50 to gnd. (6) for positive termination voltage or termination to gnd, external termination voltage must be less than 3 v below voh. for negative termination voltage, external termination voltage must be less than 2 v below voh. external termination voltage must be less than 3 v above vol. (7) at ecl levels. data out clock out
34 table 33. parameters for n4874a parbert 7 gb/s generator table 34. parameters for n4874a parbert 7 gb/s generator page 34/64 parbert 81250 main overview delay control input single-ended; dc-coupled; sma(f) input voltage window C250 mv ... +250 mv (dc-coupled) input impedance 50 typ. delay range C100 ps +100 ps modulation bandwidth dc 1 ghz @ data rate < 10.5 gb/s delay control in interface dc coupled, 50 ? nominal levels ttl levels minimum pulse width 100 ns connector sma female aux in
parbert 81250 main overview page 35/64 table 36. n4875a pattern and sequencing n4875a analyzer module the analyzer features are: ? acquire data from start ? compare and acquire data around error ? compare and count erroneous ones and zeros to calculate the bit error rate receive memory for acquired data is up to 64 mbit deep, depending on segment length resolution. the stimulus portion of the channel generates expected data and mask data. mask data is also available at the maximum segment resolution (32, 64, 128, 256, 512). the analyzer is able to synchronize on a received data stream by means of a user selectable synchroniza- tion word. the sync. word has a length of 48 bits and is composed of zeros, ones and xs (don't cares). the detect word must be unique within the data stream. synchronization on a pure prbs data-stream is done without a detect-word, instead by simply loading a number of the incoming bits into the internal prbs generator. a pre-condition for this is that the polynomial of the received prbs is known. the input comparator has differential inputs with 50 impedance. the sensitivity of 50 mv and the common mode range of the comparator allow the sampling rate 620 mhz to 7 ghz sample delay can be specified as leading edge delay in fraction of bits in each channel start delay range 0 to 100 ns fine delay range 1 period (can be changed without stopping) delay resolution 100 fs delay accuracy 10 ps 20 ppm relative to the zero-delay placement (1) relative delay accuracy 2 ps 2% typ. (1) skew between modules of same type 20 ps after cable deskewing at customer levels and unchanged system frequency. (1) analyzer auto-synchronization on prbs or memory-based data manual or automatic by: bit synchronization(2) with or without automatic phase alignment automatic delay alignment around a start sample delay (range: 10 ns) ber threshold: 10 -4 to 10 -9 (2) with prbs data, analyzers can autosyncronize on incoming prbs data bits. when using memory-based data, this data must contain a unique 48 bit detect word at the beginning of the segment, and the generators must be on a separate system clock. dont cares within detect word are possible. if several inputs synchronize, the delay diffference between terminals must be smaller than 5 segment length resolution. table 35. n4875a analyzer timing: all timing parameters are measured at ecl levels, terminated with 50 to gnd (1) 25 c - 40 c ambient temperature testing of all common differential high-speed devices. the user has the choice of using the differential input with or without a termina- tion volt age or as single-ended input (with a termination voltage). the differential mode does not need a threshold voltage, whereas the single-ended mode does. but also in differential mode the user can select one of the two inputs and compare the signal to a threshold voltage.
page 36/64 parbert 81250 main overview table 37. parameters for n4875a parbert 7 gb/s analyzer table 38. parameters for n4875a parbert 7 gb/s analyzer - clock data recovery (1) available for hardware s/n: de43a00401 and software rev. 5.62 clock data recovery the analyzer module has integrated cdr capabilities, which allow the recove ry of either clock or data. before the cdr can lock onto the incoming data stream, the data rate must be defined within the user interface; common data rates are pre-defined. in cdr mode, phase alignment to the center of the eye is done automatically during synchroni- zation. for correct operation, the cdr output must be connected to the clock input of the e4809a central clock module. in addition the generator clock source and the analyzer clock source must be independent. aux out the aux out provides data or recovered clock signals. aux in gating functionality: if a high level is applied at aux in, com- parison is disabled and internal counters are stopped. after resuming a low level at aux in, comparison is enabled and internal counters continue. the internal sequencing is not stopped. error out whenever one or more bit errors are detected, the error out signal is high for one segment resolution. a high period is always followed by a low period (rz-format) in order to ensure trigger possibility on continuous errors. common data rates s-ata: 1.5/3.0/6.0 gb/s pci-express: 2.5/5.0 gb/s oc-48: 2.488 gbit/s 10gbe: 3.125 gbit/s san: 3.187 gbit/s frequency ranges 4.23 ghz ... 6.4 ghz 2.115 ghz 3.2 ghz 1.058 ghz....1.6 ghz (1) the cdr works with specified prbs patterns up to 2 31 - 1, the cdr expects a dc balanced pattern, the cdr expects an average transition density of one transition for every second bit. number of channels 1, differential or single ended, 2.4 mm (f) range of operation 620 mb/s - 7 gb/s max input amplitude 2 vpp input sensitivity 50 mvpp typical @ 7 gb/s, prbs 2 31 - 1, and ber 10 -12 input voltage range C2v +3 (selectable 2v window) internal termination voltage (can be switched off ) C2.0 to +3.0 v (must be within selected 2 v window) threshold voltage range C2.0 to + 3.0 v (must be within selected 2 v window) threshold resolution 1 mv minimum detectable pulse width 25 ps typ. phase margin (source: n4874a) 1 ui - 12 ps typ. impedance 50 typ. ( 100 differential, if termination voltage is switched off) sampling delay resolution 100 fs data in
table 39. parameters for n4875a 7 gb/s analyzer - aux out table 40. upgrades 7 gb/s - 13 gb/s table 41. parameters for n4875a 13.5 gb/s analyzer - aux in table 42. parameters for n4875a 13.5 gb/s analyzer - error out parbert 81250 main overview page 37/64 technical specifications all specifications describe the instruments warranted perform- ance. non-warranted values are described as typical. all specifi- cations are valid from 10 to 40 c ambient temperature after a 30 minute warm-up phase, with outputs and inputs terminated with 50 to ground at ecl levels if not specified otherwise. interface ac coupled, 50 nominal amplitude 600 mv nominal output jitter (clock @ aux out) 0.01 ui rms typical connector sma female module number upgrade to 13.5 gb/s e4874a available on request e4875a available on request resolution segment resolution ttl compatible internal 500 termination to gnd threshold @ 1.5 v connector sma female low (0...1 v) internal counters are enabled high (2 v...4 v) internal counters are stopped open same as low format rz; active high output high level 0 v 100 mv output low level +1 v 100 mv connector sma female
page 38/64 parbert 81250 main overview agilent e4861b parbert 3.35 gb/s data module agilent e4862b parbert 3.35 gb/s generator front-end agilent e4863b parbert 3.35 gb/s analyzer front-end technical specifications general a parbert 3.35 gb/s module can house up to two front-ends, either two generators or analyzers or any mix. parbert 3.35 gb/s modules work with the e4808a or e4890a clock modules. the key specifications of parbert 3.35 gb/s modules are: ? 21 mhz 3.350 ghz clock/data rate ? 16 mbit memory depth at each channel ? hw-based prbs generation up to the polynomial of 2 31 -1 ? analyzer can synchronize on a 48 bit detect word (memory-based data) ? analyzer can synchronize on a pure prbs pattern without detect word timing capabilities the frequency range of the modules is 21 mhz 3.350 ghz. the parbert 3.35 gb/s front-ends use a multiplying pll that multi- plies system master clock by 4 or 8. through the clock module, an external clock source can be used. this external clock must run continuously. if the clock signal is interrupted, the multi- plying plls typically needs 100 milliseconds to lock onto the clock again. frequency range 20.834 mhz to 3.350 ghz delay = start delay + fine delay can be specified as leading edge delay in fraction of bits in each channel start delay range 0 to 200 ns (not limited by period) fine delay range 1 period (can be changed without stopping) delay resolution 1 ps accuracy data mode 25 ps 50 ppm relative to the zero-delay and temperature change within 10 c after autocalibration clock mode 50 ps 50 ppm relative to the zero-delay skew between modules of same type (data mode) 50 ps typ. after deskewing at customer levels and unchanged system frequency the variable delay is available in data mode and pulse mode. in clock mode the timing is fixed. sequencing the sequencer receives instruc- tions from the clock module. the channel sequencer can generate a sequence with up to 60 segments. an analyzer channel can gener- ate feedback signals which are combined in the clock module for a common response of all parallel channels. with a single receiver channel the channel sequencer itself handles the feedback signals. figure 23. e4861b and e4862b with waveform of e4861b generator table 43. e4861b data generator timing specification (@ 50% of amplitude, 50 to gnd)
parbert 81250 main overview page 39/64 (1) with prbs data, analyzers can autosyncronize on incoming prbs data bits. when using memory-based data, this data must contain a unique 48 bit detect word at the beginning of the segment, and the generators must be on a separate system clock. dont cares within detect word are possible. if several inputs synchromize, the delay diffference between terminals must be smaller than 5 segment length resolution. patterns memory based up to 16 mbit prbs/prws 2 n - 1, n = 7, 9, 10, 11, 15, 23, 31 mark density 1/8, 1/4, 1/2, 3/4, 7/8 at 2 n - 1, n = 7, 9, 10, 11, 15 errored prbs/prws 2 n - 1, n = 7, 9, 10, 11, 15 extended ones or zeros 2 n - 1, n = 7, 9, 10, 11, 15 clock patterns divide or multiply by 1, 2, 4 analyzer auto-synchronization on prbs or memory-based data manual or automatic by: bit synchronization(1) with or without automatic phase alignment. automatic delay alignment around a start sample delay (range: 10 ns) ber threshold: 10 -4 to 10 -9 sampling rate 20.834 mhz to 3.350 ghz sample delay same as delay = start delay + fine delay can be specified as leading edge delay in fraction of bits in each channel start delay range 0 to 200 ns (not limited by period) fine delay range 1 period (can be changed without stopping) resolution 1 ps accuracy 25 ps 50 ppm relative to the zero-delay and temperature change within 10 c after autocalibration skew 50 ps typ. after deskewing at customer levels and unchanged system frequency table 44. e4861b analyzer timing all timing parameters are measured at ecl levels, terminated with 50 to gnd table 45. e4861b pattern and sequencing
page 40/64 parbert 81250 main overview pattern generation the data stream is composed of segments. a segment can be a memory-based pattern, memory- based prbs or hardware gener- ated prbs. a total of 16 mbit (at segment length resolution 128 bits) are available for memory- based pattern and prbs. memory-based prbs is limited to 2 15 - 1 or shorter. memory-based prbs allows special prbs modes like zero substitution (also known as extended zero run) and variable mark ratio. a zero sub- stitution pattern extends the longest zero series by a user- selectable number of additional zeros. the next bit following these zero-series will be forced to 1. mark ratio is t he ratio of ones and zeros in a prbs stream, which is 1/2 in a normal prbs. variable mark ratio allows values of 1/8, 1/4, 1/2, 3/4, 7/8. due to granularity reasons a prbs has to be written to ram several times, at a multiplexing factor of 128 the number of repetitions is also 128. that means that a 2 15 - 1 prbs uses up to 4 mbit of the memory. hardware-based prbs can be any polynomial up to 2 31 - 1. no memory is used, so the total memory is free for memory- based pattern generation. error insertion allows inserting single or multiple errors into a data stream. so instead of a 0 a 1 is generated and vice versa. single errors can be inserted by pod or via instruction from the central sequencer. the user can trigger an error with a signal supplied to the qualifier pod of the central module. an error insertion with a fixed rate and a fixed distribu- tion is supported. the user soft- ware allows the selection of errored and error-free segments. almost all the combinations are possible except the following: prws port width 2 7 - 1 no restriction 2 9 - 1 7 2 10 - 1 3, 11, 31, 33 2 11 - 1 23 2 15 - 1 7, 31 2 23 - 1 47 2 31 - 1 no restriction data rate range mb/s segment length maximum memory resolution depth, bits 20.834 ... 41.666 1 bit 131,072 20.834 ... 82.333 2 bits 262,144 20.834 ... 166.666 4 bits 524,288 20.834 ... 333.333 8 bits 1,048,576 20.834 ... 666.666 16 bits 2,097,152 20.834 ... 1,333.333 32 bits 4,194,304 20.834 ... 2,700.000 64 bits 8,388,608 20.834 ... 3,350.000 128 bits 16,777,216 table 46. data rate range, segment length resolution, available memory for synchronization and fine delay operation table 47. dependancy of prws generation and port width.
parbert 81250 main overview page 41/64 outputs 1, differential or single-ended impedance 50 typ. data formats data: nrz, dnrz, rz, r1 pulse mode range sampling delay resolution width accuracy 150 ps to (1ui - 150 ps) 1 ps 40 ps typ. output voltage window C2.00 to +3.5 v (1) ext. term. voltage C2.00 to +3.5 v (2) absolute maximum external voltage C2.2 v to +3.2 v addressable technologies lvds, cml, pecl, ecl low voltage cmos amplitude/resolution 0.05 vpp ... 1.8 vpp/10 mv accuracy hi level/amplitude 2% 10 mv short circuit current 72 ma max. transition times (20% - 80%) < 75 ps; 60 ps typ. overshoot/ringing 5% +10 mv typ. jitter, nrz data mode clock mode pulse, rz, r1 mode < 30 ps peak-peak < 2 ps rms 30ps peak-peak typ. (3) (3 & 4) (3 & 4) cross-point adjustment (duty cycle distortion) 30% ... 70% (in nrz mode only) (1) for output voltages > 3 v the termination voltage 3 v needs to be applied. (2) external termination voltage must be less than 3 v below voh. and less than 3 v above vol. termination into ac is possible. (3) measured with e4808a clock module. (4) specified as intra channel jitter. generator front end (e4862b) the amplifier generates a differ- ential output signal. each output can be individually switched on and off. the output levels are suf- ficient to drive typical high-speed devices with interfaces like ecl, pecl, lvds and dvi levels. the nominal output impedance is 50 . the delay control has a single-ended input with 50 impedance. the input voltage modulates a delay element within the generators differential output. the user has the option of turn- ing the delay control in feature on or off. additionally the user can select between two delay ranges. input voltage window C500 mv to +500 mv (dc-coupled) delay range 1 C250 ps to +250 ps delay range 2 C25 ps to +25 ps modulation bandwidth dc to 200 mhz input impedance 50 (typ.) table 48. parameters for generator front-ends e4862b 3.35 gb/s table 49. delay control in
page 42/64 parbert 81250 main overview typical waveform pictures eye plots the 3.35 gb/s generator output is designed for clean and fast output signals. it offers a swing of 50 mv to 1.8 v within the voltage window suited for testing lvds, cml, (p)ecl and sstl 0 - 3.3 v technologies. figure 24a. 3.35 gb/s generator: 50 mvpp figure 24b. 3.35 gb/s generator: 1.8 v pp crossing point the 3.35 gb/s generator allows a variable cross-over for differential signals. the cross-over can be programmed by the user interface or remote program between 30 and 70%. figure 24c. 3.35 gb/s generator @30% figure 24d. 3.35 gb/s generator @50% figure 24e. 3.35 gb/s generator @70% jitter modulation examples a receiver's jitter tolerance can be tested applying a voltage at the external delay control input and by this generating jittered output signals as depicted in ? gure 26 a-d. figure 25a. jitter modulated with sine wave figure 25b. jitter modulated with rectangle wave figure 25c. jitter modulated with triangle wave figure 25d. jitter modulated with noise generator
parbert 81250 main overview page 43/64 (1) measured with e4808a central module (2) terminate with 50 to gnd, if not used analyzer front end (e4863b) the analyzer features are: ? acquire data from start ? compare and acquire data around error ? compare and count erro neous ones and zeros to calculate the bit error rate the receive memory for acquired data is up to 16 mbit deep, depending on the segment length resolution. the stimulus portion of the channel generates expect- ed data and mask data. mask data is also available at the maxi- mum granularity. the analyzer is able to synchro- nize on a received data stream by means of a user-defined detect word. the detect word is defined by the first bits within the expected segment, it has a length of 48 bits and is composed of zeros, ones and xs (dont cares). the detect word must be unique within the data stream. synchronization on a pure-prbs data-stream is done without a detect-word, by simply loading a number of the incoming bits into the internal prbs generator. a pre-condition for this is that the polynomial of the received prbs is known. the input comparator has differ- ential inputs with 50 imped- ance. the sensitivity is down to 50 mv and the common mode range of the comparator allows the testing of all common differ- ential high-speed devices.the user has the option of using the differential input with or without a termination voltage or as sin- gle-ended input (with a termina- tion voltage). the differential mode does not need a threshold voltage, whereas the single-ended mode does. but also in differen- tial mode the user can select one of the two inputs and compare the signal to a threshold voltage. protection input and output relays switch off automatically, if the absolute maximum voltage window is exceeded. figure 26. eye diagram of e4863b analyzer table 50. parameters for analyzer front-ends e4863b 3.35 gb/s number of channels 1, differential or single-ended impedance 50 typ. (100 differential if termination voltage is switched off) internal termination voltage (can be switched off) -2.0 to +3.0 v threshold voltage range -2.0 to +3.0 v threshold resolution 1 mv threshold accuracy 20 mv 1% input sensitivity (single-ended and differential) < 50 mv minimum detectable pulse width < 150 ps maximum input voltage range three ranges selectable: -2 v to +1 v -1 v to +2 v 0 v to 3 v maximum differential voltage 1.8 v phase margin with ideal input signal > 1 ui - 30 ps (1) phase margin with e4862b generator > 1 ui - 50 ps (1) auxilary out v out: 350 mv pp typ., ac coupled (2) sampling delay resolution 1 ps
page 44/64 parbert 81250 main overview e4832a 675 mb/s generator/analyzer module this module holds any combina- tion of up to two analyzer front- end pairs (e4835a) and four gen- erator front-ends (e4838a). clock module/data mode the generator can operate in clock mode or data mode. clock mode is achieved when the gen- erator is assigned as a pulse port. data mode is achieved with assigning it to a data port. in clock mode it is a fixed duty cycle of 50%. in data mode it is nrz format with variable delay. the analyzer only works as a data port whenever used with variable sampling delay. the sampling delay consists of two elements: the start delay and the fine delay. the fine delay can be varied within 1 period without stopping. data capabilities prbs/prws and memory-based data are defined by segments. segments are assigned to a gen- erator, and for stimulating a pat- tern. on an analyzer, it defines the expected pattern which the incoming data are compared to. the expected pattern can contain mask bits. agilent e4832a parbert 675 mb/s data module agilent e4838a parbert 675 mb/s generator front-end agilent e4835a parbert 675 mb/s analyzer front-end technical specifications 4 slots for the front-ends e4835a(1), e4 838a (1) pairs occupy two front-end slots of the e4832a e4832a generator/ analyzer 675 mbit/s module figure 27. e4832a module the segment length resolution is the resolution to which the length of a pattern segment can be set. the maximum memory per channel of the e4832a can be set in steps of 16 bits up to a length of 2048 kbit. if the 16-bit segment length resolution is too coarse, memory depth and frequency can be traded. sub-frequencies for applications requiring differ- ent frequencies at a fraction of the system clock, the ratio can be divided or multiplied by 2, 4, 8, or 16. this influences the dependency between segment length resolution and maximum memory depth. fig 28. wave diagram of e4832a generator
parbert 81250 main overview page 45/64 synchronization synchronization is the method of automatically adjusting the prop- er bit phase for data comparison on the incoming bit stream. the sychronization can be performed on prbs/prws and memory- based data but it is not possible on a mix of prxs and memory based data. there are two types of synchronization: ? bit synchronization ? auto delay alignment bit synchronization is possible to cover a bit alignment for a totally unknown number of cycles. using memory-based data, the first 48 bits within the expected data seg- ment will work as a detect word which the incoming data are compared to. when the incoming data match with this detect word, analysis will begin. auto delay alignment is per- formed by using the analyzer sampling delay. the sampling delay range is 50 ns while this is possible. using auto delay alignment pro- vides synchronization with an absolute timing relation between a group of analyzer channels. this makes skew measurements are possible. frequency range 333,334 khz to 675 mhz delay range 0 to 3.0 s (not limited by period) sampling delay resolution 2 ps accuracy 50 ps 50 ppm relative to the zero-delay placement (1) skew 50 ps typ. after deskewing at customer levels pulse width can be specified as width or % of duty cycle range 750 ps to (period -750 ps) resolution 2 ps accuracy 200 ps 0.1% duty cycle 1% to 99%, subject to width limits sample delay = start delay + fine delay fine delay can be changed without stopping (2) sampling rate (3) 333,334 kb/s to 675 mb/s sampling delay ( = start delay + fine delay) range 0 to 3.0 s (not limited by period) fine delay range 1 period accuracy 50 ps 50 ppm relative to the zero-delay placement (3) resolution 2 ps skew 50 ps typ. after deskewing at customer levels (1) valid at 15 to 35 oc room temperature (2) conditions: frequency > 20.8 mhz and by using the finest segment length resolution. (3) see tables for front-end deratings table 51. e4832a data generator timing specifications (@ 50% of amplitude, 50 to gnd and fastest transition times) table 52. e4832a analyzer timing; all timing parameters are measured at ecl levels terminated with 50 to gnd
patterns: memory based up to 2 mbit prbs/prws 2 n - 1, n = 7, 9, 10, 11, 15, 23, 31 mark density 1/8, 1/4, 1/2, 3/4, 7/8 at 2 n - 1, n = 7, 9, 10, 11, 15 errored prbs/prws 2 n - 1, n = 7, 9, 10, 11, 15 extended ones or zeros 2 n - 1, n = 7, 9, 10, 11, 15 clock patterns divide or multiply by 1, 2, 4 user patterns data editor, file import analyzer auto-synchronization (2): on prbs or memory-based data manual or automatic by: bit synchronization (1) with or without automatic phase alignment automatic delay alignment around start sample delay (range: 50 ns) ber threshold: 10 -4 to 10 -9 prws port width 2 7 - 1 no restriction 2 9 - 1 7 2 10 - 1 3, 11, 31, 33 2 11 - 1 23 2 15 - 1 7, 31 2 23 - 1 47 2 31 - 1 no restriction data rate range mb/s segment length maximum memory resolution depth, bits 20.834 ... 41.666 1 bit 131,008 41.667 ... 83.333 2 bits 262,016 83.334 ... 166.666 4 bits 524,032 166.667 ... 333.333 8 bits 1,048,064 333.334 ... 666.667 16 bits 2,097,152 in general, it is possible to set higher values for the segment length resolution and also at lower frequencies than are indicated in the table. in this case the fine delay function and the auto-synchronization function are unavailable. (1) bit synchronization on data is achieved by detecting a 48 bit unique word at the beginning of the segment. dont cares within the detect word are possible. in this mode no memory-based data can be sent within the same system. if several inputs synchronize, the delay difference between the terminals must be 5 segment length resolution. (2) condition: frequency > 20.8 mhz and by using the finest segment length resolution. page 46/64 parbert 81250 main overview table 53. pattern and sequencing features of e4832a table 54. data rate range, segment length resolution, available memory for synchronization and fine delay operation table 55. between the capability of generating prws and port width, almost all the combinations are possible except the following:
parbert 81250 main overview page 47/64 input/output addressable technologies lvds, (p)ecl, ttl, 3.3 v cmos analyzer input the analyzer channel can be operated: ? single-ended normal ? single-ended compliment ? differential for termination there is always 50 connected to a programmable termination voltage. in differential mode there is an additional, selectable 100 differential ter- mination. independent of the selected termination, there is the choice of whether the anaylsis of the incoming signal is performed on the input or true differential. number of channels 1, differential impedance 50 typ. data formats rz, r1, nrz, dnrz output voltage window C2.2 to +4.4 v (doubles into open up to max. 5 vpp) amplitude/resolution 0.1 v to 3.50 v / 10 mv level accuracy 3% 25 mv typ. after 5 ns settling time @ lvds/(p)ecl 1% 25 mv typ. after 5 ns settling time variable transition time range (10 - 90% of amplitude) 0.5 to 4.5 ns accuracy 5% 100 ps @ lvds/(p)ecl (20 - 80% of amplitude) 0.35 ns typ overshoot/ringing < 7% (< 5% typ). jitter data mode clock mode < 100 ps peak to peak (80 ps typ) 8 ps rms typ. channel addition xor and analog figure 29. eye diagram of e4835a analyzer table 56. level parameters for differential generator front-end e4838a 675 mb/s
page 48/64 parbert 81250 main overview (1) occupy two front-end slots of the e4832a. the e4835a contains two front-ends (e4835az) and one common data back end. in this document one front-end is referred to as e4835a. number of channels 2, differential or single-ended (switchable) impedance 50 typ. 100 differential if termination voltage is switched off termination voltage (can be switched off) C2.0 to +3.0 v threshold voltage range/ threshold accuracy C2.00 to +4.50 v/1% 20 mv threshold resolution 2 mv input sensitivity differential 50 mv typ single-ended 100 mv typ minimum detectable pulsewidth 400 ps typ. at ecl levels input voltage range two ranges selectable: 0 to +5 v and -2 to +3 v phase margin with ideal input signal with e4838a generator > 1 ui - 100 ps > 1 ui - 180 ps table 57. two differential analyzer front-ends e4835a (1), 667 msa/s
parbert 81250 main overview page 49/64 each parbert 81250 system consists of at least one clock module, which generates the system clock for at least one generator or analyzer or any mix. please see the table to the right for a complete compatibility overview. sequencing the sequencing can be used to specify the data flow: ? single ? looped ? i nfinite loop ? event handling (branch) ? synchronization event handling with event handling, the flow of data generation and analysis can be controlled with external signals at run time. usage of events ? start and stop of data ? match loop ? integration with other equipment (ate) ? trigger on error agilent e4809a 13.5 ghz central clock module agilent e4808a high performance central clock module agilent e4805b 675 mhz central clock module technical specifications modules/central clock e4805b e4808a e4809a e4832a - parbert 675 mb/s e4861a - parbert 2.7/1.6 gb/s e4861b - parbert 3.35 gb/s e4810a/11a - parbert 3.3.5 gb/s optical (1) e4866a/67a - parbert 10.8 gb/s (1) n4872a/73a - parbert 13.5 gb/s e4868b/69b - parbert 45 gb/s (1) e4874a/75a - parbert 7 gb/s number of segms ents 1 to 30 (every segment looped once) 1 to 60 (no segment looped) looping levels up to 4 nested loops plus one optional infinite loop loops can be set independently from 1 to 2 20 repetitions start/stop external input, manual, programmed (stop with e4832a only) event handling react on internal and external events. event trigger sources events can be defined as any combination of the following sources. a maximum of 10 events can be defined. 8-line trigger input pod for ttl signals vxi trigger lines to and t1 any capture error/or no error detected by one of the analyzer channels software command control: an event trigger command issued locally or remotely reactions to an event can be set per data segment immediately or deferred and can be any combination of: data segment jump launch trigger pulse at trigger output of the clock module vxi trigger lines to and t1 can be set to 01, 10, or 11 agilent parbert 81250 central clock modules table 58. table 59. e4809a, e4808a and e4805b sequencing features table 60. e4809a, e4808a and e4805b event handling (1) modules discontinued.
page 50/64 parbert 81250 main overview table 61. e4809a, e4808a and e4805b trigger pod characteristics table 62. e4809a clock module specifications master slave, multi-mainframe, different clock groups up to 3 clock modules can be combined to run in one clock grouping by connecting the mas- ter slave cable. this is used to combine channels which do not fit into one frame into one clock group. omitting the master-slave connection will run the channels as separate clock groups. a system can be a combination of multiple clock groups made up of multiple channels. the frequencies used can be totally asynchronous or m/n ratio (see clock input multiplier/divider). for separated clock groups the master slave is not used. within one master-slave system the modules must be the same type. input lines 8, single-ended input levels ttl compatible input threshold 1.5 v input termination 5 k pullup to +5 v absolute max ratings for input voltages C1.2 v to + 7.0 v cable delay 11 ns typical sampling clock frequency system frequency/segment length resolution setup time (1) hold time (1) trigger output 2.5 ns 5 ns clock/ref input C12.5 ns 20 ns frequency range 20.834 mhz13,5 ghz resolution 1 hz ssb phase noise (at 10 khz offset) < -75 dbc at 10 ghz latency external start input ? start in to trig out with 7/13.5 gb/s ? start in to data out with 7/13.5 gb/s ? in to trig out without 7/13.5 gb/s ? in to data out without 7/13.5 gb/s 16 ns + (2 * system clock * segment resolution) 1 clock (1) 416 ns + (2 * system clock * segment resolution) 1 clock (1) 16 ns 1 clock (1) 48 ns 1 clock (1) figure 30. e4809a module general e4809a is a 2-slot central clock module with 13ghz clock distribu- tion. parbert 81250 13.5 gb/s modules are designed to run with the e4809a 13.5 ghz central clock module. start in e4809a 13.5 ghz central clock module giga clock clocks for expander frames system clock outputs clock input trigger output 10 mhz reference in de-skew probe trigger pod master/slave connection ( 1) includes the cable delay (1) add 3 ns if expander frame is used
parbert 81250 main overview page 51/64 table 63. start input ttable 64. reference input timing capabilities the e4809a supports three different operation modes. e4809a as system clock the e4809a distributes clock signals to connected modules in the range from 20.834 mhz up to 13.5 ghz. the e4809a provides giga-clock signals in a range from 500 mhz up to 13.5 ghz to the parbert 81250 13.5 gb/s modules (n4872a, n4873a). all other supported modules work using the e4809a master clock. external clock mode the system will run synchro- nously to an external clock, which is connected to the clock module's clock input. there are two different sub-modes availa- ble. in the direct clock mode, the pll (phase locked loop) is bypassed and an external clock signal can be distributed to all giga-clock connected modules. this direct external clock mode operates in a range from 500 mhz to 13.5 ghz. in this mode the external clock may be fm or pm modulated. in the indirect external clock mode, the clock modules internal pll is used to generate flexible master clock and giga-clock signals. clock data recovery (cdr) mode if the cdr is used, the cdr out of the analyzer must be connect- ed to the clock input of the clock module. start input a sequence of generated data can be started by an external signal. start input dc coupled; 3.5 mm (f) threshold range C1.40 v to +3,70 v zin/termination voltage 50 typ./-2 v to +3 v sensitivity/max. levels 200 mvpp / -3 v+6 v reference input the reference input allows parbert to run synchronously with an external 10 mhz clock. a continuous clock is necessary. a burst clock can not be used as an external clock. reference input ac coupled; 3.5 mm(f) frequency 10 mhz input transition time < 20 ns required duty cycle 50% 10 imput impedence 50 sensitivity 200 mvpp required input phase noise table 65. clock input table 66. trigger input clock input this input runs parbert syn- chronously with an external clock. usage of a continuous clock is necessary. a burst clock can not be used as an external clock. two modes are selectable: indirect external clock mode (clock module pll is used) and direct external clock mode (clock module is bypassed). clock input ac coupled; 3.5 mm (f) frequency range indirect mode direct mode 20.834 mhz13.5 ghz 620 mhz13.5 ghz clock input (indirect mode only) multiplier(m)/divider(n) m = 1256; n = 1256 m x n < = 1024; clock > = 5 mhz input transition/slope 30 ps typ. zin 50 sensitivity < 150 mv required input phase noise < 75 - 20 log (13.5 ghz / input frequency) dbc / hz trigger output the trigger output is used to deliver a trigger signal to a dut, a digital communication analyzer (agilent 86100a/b/c series) or as a stimulus for the analyzer de-skew. trigger output dc coupled, sma (f) frequency up to 675 mhz output transition/slope 70 ps typ. 10/90 zout/termination voltage 50 /-2 to +3 v output voltage window C2 v to +3 v output level 0.1 to 1.8 vpp page 52/64 parbert 81250 main overview
parbert 81250 main overview page 53/64 table 67. e4805b and e4808a clock module specifications e4805b and e4808a central clock modules the central clock module includes a pll (phase-locked loop) frequency generator to pro- vide a system clock. depending on the frequency chosen, the data modules can be clocked at a ratio of 1, 2, 4, 8, 16, 32, 64 or 256 times higher or lower than the system clock. external start/stop: the data can be started by an external signal applied to the external input. when using the e4832a module, a stop mode and a gate mode is also available. clock outputs for modules clock for expander frames clock/ref. input external input trigger output deskew probe figure 33: clock module trigger pod input. master- slave connection e4805b e4808b frequency range (1) (can be entered as period or frequency) 1 khz to 675 mhz 170 khz to 675 mhz will run with ? e4861a (2) in range of 334 mhz to 2.7ghz ? e4832a in range of 334 khz to 675 mhz ? e4866a/e4867a (2) in range of 9.5 ghz to 10.8 ghz ? e4861b in range of 20.834 mhz to 3.35 ghz ? e4861a (2) in range of 334 mhz to 2.7 ghz ? e4832a in range of 334 khz to 675 mhz resolution 1 hz 1 hz accuracy 50 ppm with internal pll reference 50 ppm with internal pll reference (1) may be limited or enhanced by modules or frontends (2) modules discontinued ext. clock/ext. reference: this input runs parbert 81250 synchronously with an ext. clock, or when a more accurate reference is needed than the internal oscillator. a continuous clock is necessary. a burst clock cannot be used as an external clock. maximum external clock is 2.7 ghz for the e4805b and 10.8 gb/s for the e4808a. (note: no improvement of jitter specifi- cations will be achieved with an external clock). guided de-skew: individual semi- automatic deskew per channel is available. the 15447a de-skew probe 15447a allows de-skew on the dut's (device under test) fixture.
table 68. external input and ext. clock/ext. ref. input table 69. trigger output characteristics e4805b and e4808a trigger ouput can be used in: ? clock mode ? sequence mode in sequence mode a pulse will be set to mark the start of any segment. in clock mode, the trigger output can supply a clock output of up to 675 mhz. if a higher speed performance clock is needed: ? a 2.7 gb/s generator can be used to supply a clock output up to 2.7 ghz ? a 10.8 gb/s generator can be used to supply a clock output up to 10.8 ghz. trigger output signals ? clock mode (up to 675 mhz). ? sequence mode output impedance 50 typ. output level ttl (frequency < 180 mhz), 50 to gnd ecl 50 to gnd/-2 v, pecl 50 +3 v trigger advance 30 ns typ. between trigger output and data output /sampling point (delay set to zero in both cases) maximum ext voltage C2 v to +3.3 v jitter (int. reference/int. clock) < 10 ps rms (5 ps typ.) technical specifications all specifications describe the instruments warranted performance. non-warranted values are described as typical. all specifications are valid from 10 to 40 ambient temperature after a 30 minute warm-up phase, with outputs and inputs terminated with 50 ohms to ground at ecl levels unless specified otherwise. e4805b e4808a zin/termination voltage 50 /-2.10 v to 3.30 v 50 /-2.10 v to 3.30 v sensitivity/max levels 400 mvpp/-3 v to + 6 v 200 mvpp/-3 v to + 6v for < 9.5 gbit/s 300 mvpp/-3 v to+ 6 v for > 9.5 gb/s coupling dc dc ext. input: threshold range: C1.40 v to +3.70 v C1.40 v to +3.70 v ext. clock/ext. ref: ac ac input transitions/slope < 20 ns. ext. input active edge is selectable < 20 ns. ext. input active edge is selectable clock input multiplier(m)/divider (n) m = 1...256; n = 1...256 m*n < = 1024 m/n * input frequency must fit data range input frequency/n > = 1.3 mhz pll lock time 100 ms 100 ms input frequency/period ext. clock 170 khz - 2.7 ghz 170 khz - 10.8 ghz ext. ref 1(1), 2(1), 5, or 10 mhz 1(1), 2(1), 5, or 10 mhz required duty cycle 50 10 % 50 10 % latency (typical): to trigger output to channel output to trigger output to trigger output ext. input 16ns 1 clock 46ns 1 clock 16 ns 1 clock 46 ns 1 clock(2) ext. clock 15 ns 45 ns 15 ns 45 ns add 3 ns if an expander frame is used add 3 ns if an expander frame is used (1) jitter performance may be degraded (2) if frequency = 667 mhz page 54/64 parbert 81250 main overview
parbert 81250 main overview page 55/64 table 70. programming times table 71. cooling requirements for modules with front-ends installed general characteristics mainframes: see table 72 on page 56. save/recall: pattern segments, settings and complete settings plus segments can be saved and recalled. the number of settings that can be stored is limited only by disk space. vector import/export: file format is ascii using a stil subset. import/export to/from parbert internal data-base for regular file transfer via usb memory stick, cd or lan is handled by parbert user sw. direct programming of data segments is possible via gpib (ieee 488.2) and scpi. programming interface: gp-ib (ieee 488.2) and lan. the interface to applications such as c, visual basic, or vee must be installed. use the agilent 81200 plug&play drivers for easy programming. programming language: scpi 1992.0, active x for mui programming times: vector transfer from memory to hardware depends on the amount of data. see table 70 for examples. on-line help: context-sensitive. print-on-demand: getting started and programming guides can be printed from .pdf files included in the parbert 81250 software. self-test: module and system selftests can be initiated. modules module size: vxi c-size, 1 slot. module type: register-based; requires parbert 81250 user software e4875a supplied with the mainframes. weight: (including front-ends) net: 2kg. shipping: 2.5 kg. warranty: 1 year return to agilent re-calibration period: 1 year. agilent technologies quality standards the parbert 81250 is produced in accordance to the iso 9001 international quality system standard as part of agilent technologies commitment to continually increasing customer satisfaction through improved quality control. parameter programming time for one e4805b with one e4832a. increases with the number of modules. change of levels 6 ms typ. change of delay 16 ms typ. not applicable in run mode change of period (1) 60 ms typ. not applicable in run mode. stop & start 32 ms typ. synchronization (1) 50 ms typ. (without phase alignment) 110 ms typ. with 20% phase accuracy @ 660 mhz 650 ms typ. with 1% phase accuracy @ 660 mhz download values system with 4 channels < 1.5 s typ. 1000,000 bit each system with 120 channels < 20 s typ. 1 mbit each system with 40 channels < 10 s typ. 1 mbit each modules ?p mm h2o air flow liter/s max ?temp e4805b 0.25 3.6 10 c e4808a 0.25 3.6 10 c e4809a 1.08 3.7 12 c e4832a 0.30 4.7 15 c e4861b 0.40 6.6 15 c n4872a/74a 1.20 7.5 13 c n4873a/75a 0.85 5.4 12 c (1) valid for a system consisting of one e4805a and one e4832a.
page 56/64 parbert 81250 main overview table 72. power requirements of modules and front-ends dc volts +24v +12v +5v C2v C5.2v C12v C24v modules (these specifications are valid for the module with the front-ends installed) e4805b central clock module dc current dynamic current 0.15a 0.015a 0.2a 0.02a 1.8a 0.18a 1.4a 0.14a 3.8a 0.38a 0.2a 0.02a C C e4808a dc current dynamic current 0.2a 0.02a 0.3 a. 0.03a 1.8a 0.18a 1.9a 0.19a 3.9a 0.39a 0.2a 0.02a C C e4809a dc current dynamic current 0.35a 0.05a 1.25 a 0.15a 2.0a 0.2a 2.4a 0.3a 6.8a 0.7a 0.5a 0.05a 0.55a 0.06a n4872a/74a dc current dynamic current 0.5a 0.05a 0.75a 0.08a 3.8a 0.38a 0.6a 0.06a 2.6a 0.26a 1.2a 0.12a 0.8a 0.08a n4873a/75a dc current dynamic current 0.2a 0.02a 0.5a 0.05a 4.6a 0.46a 0.7a 0.07a 2.3a 0.23a 0.3a 0.03a 0.7a 0.07a e4861b dc current dynamic current 0.02a 0.01a 0.03a 0.01a 2.2a 0.2a 0.4a 0.04a 0.4a 0.04a C C C C e4862b generator dc current dynamic current 0.2a 0.02a 0.2a 0.02a 1.0a 0.07a 0.2a 0.02a 0.5a 0.05a 0.21a 0.2a 0.48a 0.05a e4863b analyzer dc current dynamic current 0.2a 0.02a 0.2a 0.02a 2.0a 0.02a 0.2a 0.02a 0.45a 0.05a 0.21a 0.2a 0.48a 0.05a e4832a 675 mb/s gen./an. module dc current dynamic current 0.10a 0.01a 0.10a 0.01a 2.60a 0.26a 0.60a 0.06a 3.60a 0.36a 0.10a 0.01a 0.1a 0.01a remark: for the module e4832a, the power specifications of the chosen front-ends (e4835a, e4838a or e4843a) have to be added to the power specifications of the e4832a module to get the overall value of the power specifications e4838a differential generator 675 mb/s dynamic current dc current 0.45a 0.045a 0.18a 0.018a 0.07a 0.007a 0.38a 0.038a 0.41a 0.041a C C front-ends e4835a two differential analyzer 675 mb/s dc current dynamic current 0.2a 0.02a 1.2a 0.12a 0.2a 0.02a 0.3 a 0.03a 0.3a 0.03a C C
parbert 81250 main overview page 57/64 table 73. general mainframe characteristics 81250a mainframe description e8403a 13 slot vxi c-size frame order description 81250a-149 (entry frame) 81250a-152 (expander frame) 81250a-148 number of slots available for parbert 81250 data/ clock modules 12 operating temperature 10 c to 40 c storage temperature -20 c to +60 c humidity 80% rel. humidity at 40 c power requirements 90 - 264 vac 47 - 66 hz 90 - 264 vac 300 - 440 hz (not recommended: leakage current may exceed safety limits @ > 132 vac) power available for modules 950 w for 90 - 110 vac supplies 1000 w for 110 - 264 vac supplies electromagnetic compatibility en 55011/cispr 11 group 1, class a + 26 db acoustic noise 48 (56) dba sound pressure at low (high fan speed) safety iec 348, ul 1244, csa 22.2 #231, ce-mark physical dimensions w: 424.5 mm, 16.71 inches h: 352 mm, 13.85 inches d: 631 mm, 24.84 inches weight (net) 26.8 kg (25.3 kg) weight (shipping) (max.) 72 kg (67 kg)
page 58/64 parbert 81250 main overview table 74. ordering guide the parbert 81250 is a modular instrument, which can be tailored to your specific needs. it consists of the user sw and modules. these can be categorized by their functionality (clock or data) and their maximum data rate (675mb/s, 3.35gb/s and 7/13.5gb/s). the 675mb/s data modules can hold up to four generator or analyzer front-ends allowing either four generator- or analyzer- channels or two channels of each kind. the 3.35gb/s modules can hold two front-ends of any combination, resulting in two channels. the 7gb/s and 13gb/s modules are dedicated generator or analyzer modules delivering one data channel. entry system a minimum system consists of one clock module and one data module forming a so-called clock group which gets installed in the parbert vxi-mainframe. the connection between the pc (81250 #015, a laptop), which runs the user sw, and the vxi- frame, which holds the the parbert hardware, is achieved by the so called slot-0 controller, in this case an ieee1394 firewire interface, 81250 #013, which consumes 1 of the 13 slots of the vxi-frame. the mainframe can hold multiple clock groups. each is operated by its own instance of the graphi- cal user interface (gui). assuming the use of the firewire interface and one clock module in place, the entry system can hold up to: ? 10 channels at 13.5 gb/s and 7 gb/s ? 22 channels at 3.35 gb/s ? 44 channels at 675 mb/s. in some circumstances these maximum numbers cannot be achieved due to power restric- tions. before finalizing a configu- ration, it is necessary to calcu- late the power budget. the 675 mb/s analyzer e4835a always comes as a pair and need to be configured side by side, providing two fully independent analyzer channels. quick ordering guide - overview data module/front-ends generator analyzer clock module 13.5 gb/s data module 7 gb/s data module n4872b n4874a n4873 n4875a e4809a e4809a 3.35 gb/s data module 3.35 gb/s front-end (1) e4861b e4862b e4861b e4863b e4808a or e4809a 675 mhz data module 675 mhz front-end (2) (3) e4832a e4838a e4832a e4835a e4805b or e4808a or e4809a max # of channels firewire 675 mbits 3.35 gb/s 7 or 13.5 gb/s 1 frame 44 22 10 2 frames 88 44 20 3 frames 132 66 30 4 frames 176 88 40 more than 3 frames require more than one clock group. (1) houses 2 front-ends (2) houses 4 front-ends (3) e4835a provides a pair of analyzers table 75. entry system
parbert 81250 main overview page 59/64 multi-mainframe/master-slave if the number of desired channels exceeds the number of available slots in the entry frame, it is possible to add expander frames. to add channels within one clock group, there is the limit of a maximum of two expander frames. if data modules are housed in an expander frame they need an additional clock module. this clock module must be connected to the clock module in the entry frame (master frame) with the help of the master-slave connection. this connection car- ries the clock and data flow syn- chronization between the frames. the master-slave connection hardware is delivered with the expander frames. the master- slave connection is only possible between clock modules of the same type. aside from the master-slave con- nection between the clock mod- ules, the controller interface also needs an extension into the expander frames: the firewire interface, can be daisy-chained from frame to frame. this would allow the configuration of a parbert 81250 system with a virtually unlimited number of channels. however, as mentioned above, a clock group can only be constructed of up to three vxi-frames, such that parbert systems larger than three frames must consist of more than one- clock group. different clock groups a clock group consists of a clock module and one or more data modules. it is possible to have data modules from different speed classes combined in one clock group. the configuration of more than one clock group is possible. several clock groups may be housed in one frame. using expander frames is also possible. each clock group will be operated from an independent instance of the graphical user interface, which will actually be assigned to this set of hardware defined as a clock group. in such a case the different guis may run from separate pcs, connect- ed via lan. a configuration of more than one clock group is recommended for the following purposes: ? to run different speeds (non binary ratio) between generators and/or analyzers ? to make flexible use of data rate range when combining different speed classes ? to use custom (memory) based data and use of bit synchronization for the analyzer(s). the additional clock modules necessary for the different clock groups reduce the maximum number of possible channels listed in table 85 on the previous page. a master-slave connection must not be installed between the clock modules if different clock groups are desired.
order information entry system 1 x 81250a 1 x 81250-149 1 x e4805b-ato/e4808a-ato/ e4809a-ato system reference mainframe 1st clock module decide on controller: 1 x 81250a-013 1 x 81250a-014 or 1 x 81250a-015 firewire (ieee 1394) pc link to vxi ext. pc laptop including pcmcia ieee 1394 card decide on controller accessories: 1 x 15444a 1 x 15445a monitor ext. cd-rom order information multi mainframe: 1 x 81250-152 1 x e4805b/e4808a/ firewire (ieee 1394) expander frame clock module order information master-slave/different clock groups e4805b-ato: clock module (usable with 675mb/s and 2.7 gb/s module) e4808a-ato: clock module (usable with 675 mb/s, 1.65 gb/s, 2.7 gb/s, 3.35 gb/s, 10.8 gb/s and 45 gb/s modules) e4809a-ato: clock module (usable with 675 mb/s, 3.35 gb/s, 7 gb/s and 13.5 gb/s modules) specific rules: do not mix e4809a, e4808a and e4805b: ? slave connection is possible only between clock modules of the same type ? one system must be configured with one type of clock module add data modules/front-ends p/n cable kit description no. of cables connectors to be used with bandwidth matching length addl. parts included 15441a sma to sci 10 sma (m) - sci (f) 675 mb/s tt 500 ps no 1.5 m 4 sci adapt- ers 15442a sma 4 sma (m) - sma (m) 675 mb/s/ (3.35*) gb/s tt 100 ps no 1 m C 15443 sma matched pair 2 sma (m) - sma (m) 675 mb/s/ (3.35*) gb/s tt 100 ps yes 1 m C n4869a sma & phase shifter 3 sma (m) - sma (m) e4866a out to n4868a in tt 50 ps adjustable 0.4 m mech. phase shifter 50 ps n4870a 1.85 mm matched 2 1.85/2.4 mm 1.85/2.4 mm n4868a out e4868a/b out e4869a/b in tt 15 ps 1.5 ps 0.63 m C n4871a sma matched 2 sma (m) - sma (m) 3.35 gb/s front-ends tt 50 ps 1.5 ps 1 m C n4910a 2.4 mm matched pair 2 2.4 mm - 2.4 mm 7 gb/s, 13.5 gb/s 0.60 m C page 60/64 parbert 81250 main overview table 76. cable kit accessories
parbert 81250 main overview page 61/64 part #/option description 81250a parbert 81250 81250a-013 ieee 1394 pc link to vxi 81250a-015 laptop including pcmcia ieee 1394 card 81250a-148 13-slot vxi mainframe 81250a-149 mainframe 81250a-152 ieee 1394 'firewire' expander frame 81250a-0b0 do not include tutorial cd rom 81250a-ax4 rack flange kit software e4875a-ato one licence and software cd rom for parbert 81250 clock modules e4805b 675 mhz central clock module e4808a high performance central clock module e4809a 13.5 ghz central clock module data modules & front ends e4832a-ato 675 mb/s generator/analyzer module e4835a-fg two differential analyzer front-ends, 675 mb/s e4838a-fg differential generator front-end, 675 mb/s e4861b-ato 3.35 gb/s generator/analyzer module e4862b-ato generator front-end 3.35 gb/s e4863b-ato analyzer front-end 3.35 gb/s n4874a-ato generator module 7 gb/s n4875a-ato analyzer module 7 gb/s n4872a-ato generator module 13.5 gb/s n4873a-ato analyzer module 13.5 gb/s hdmi bundles and accessories e4887a-003 economic hdmi signal generator up to 3.4 gb/s e4887a-007 hdmi tmds signal generator up to 7 gb/s e4887a-037 hdmi tmds signal generator up to 3.4 gb/s e4887a-101 cts 1.3 compliant low-speed cable emulator (< 75mhz) e4887a-102 cts 1.3 compliant high-speed cable emulator (> 75mhz) e4887a-104 cts 1.3 compliant passive eq type cable emulator (set of 8 units) e4887a-207 hdmi frame generator software for e4887a platform e4887a-303 accessory and cable kit for e4887a-003 hdmi signal generator e4887a-307 accessory and cable kit for e4887a-007 tmds signal generator 7 gb/s e4887a-308 accessory and cable kit for e4887a-007 hdmi tmds signal generator e4887a-310 accessory and cable kit for e4887a-037 hdmi tmds signal generator e4887a-s01 cts 1.3 compliant passice eq type cable emulator prototype (5mm chip) product structure - parbert 81250
page 62/64 parbert 81250 main overview accessories 15440a adapter kit: 4* sma (m) i/o adapters 15442a cable kit: 4*sma (m) to sma (m) 15443a matched cable pair 15446a 8-line trigger input pod 15447a deskew probe n4871a cable kit: sma matched pair, 50 ps n4910a cable kit: matched cable pair for 13.5 g n4911a-002 adapter 3.5 mm female to 2.4 mm male n4912a 2.4 mm 50 termination, male connector n4913a 4 ghz deskew probe test automation software platform n5990 (excerpt) n5990a-010 test automation software platform, required for all other options n5990a-001 interfaces to databases (microsoft sql and mysql) and web browsers n5990a-500 user programming (api including templates) for test interfaces pls see www.agilent.com/find/automation warranty & services all systems and modules have 1 year on-site warranty. start up assistance for first time users is included. product structure - parbert 81250 (continued)
this statement is to certify that none of agilent technologies parbert 81250 clock modules, data generator/analyzer modules or front ends store customer speci? c data in any non-volatile memory. as a general rule it can be said that after electrical power has been turned off, the modules will not store any data or settings. data storage across power down/power up cycles will only appear in the parberts pc controller where access to the data can be controlled via generic microsoft ? windows ? security mechanisms. storage of customer speci? c data in parbert 81250 modules and front ends related literature ? agilent parbert 81250, mux/demux application, application note, literature number 5968-9695e ? advanced memory buffer, product note, literature number 5989-3481en ? jitter fundamentals: jitter tolerance testing with agilent 81250 parbert, application note, literature number 5989-0223en ? hdmi compliant jitter tolerance test solution for cable and rx test with parbert 81250, application note, literature number 5989-4959en ? how to characterize the physical layer of the mobile industry processor interface (mipi d-phy), application note literature number, 5989-7184en ? next generation i/o bus pci-express ber test solution application note, literature number 5989-2690en ? automated pci express receiver compliance test and characterization with the agilent n5990a software platform, application note, literature number 5989-5500en ? agilent n5990a test automation software platform (version 1.0), product overview, literature number 5989-3797en ? test automation software platform n5990a, data sheet, literature number 5989-5483en ? total jitter measurement at low probability levels using optimized bert scan method, white paper, literature number 5989-2933en ? fast total jitter test solution, application note, literature number 5989-3151en ? bert family brochure - applications focused, brochure, literature number 5988-9514en ? physical layer testing of passive optical network (pon) modules, application note, literature number 5989-3298en parbert 81250 main overview page 63/64
www.agilent.com/? nd/emailupdates get the latest information on the products and applications you select. www.agilent.com/? nd/agilentdirect quickly choose and use your test equipment solutions with con? dence. www.agilent.com www.agilent.com/? nd/parbert- for more information on agilent technologies products, applications or services, please contact your local agilent of? ce. the complete list is available at: www.agilent.com/? nd/contactus americas canada (877) 894-4414 latin america 305 269 7500 united states (800) 829-4444 asia paci? c australia 1 800 629 485 china 800 810 0189 hong kong 800 938 693 india 1 800 112 929 japan 0120 (421) 345 korea 080 769 0800 malaysia 1 800 888 848 singapore 1 800 375 8100 taiwan 0800 047 866 thailand 1 800 226 008 europe & middle east austria 01 36027 71571 belgium 32 (0) 2 404 93 40 denmark 45 70 13 15 15 finland 358 (0) 10 855 2100 france 0825 010 700* *0.125 /minute germany 07031 464 6333** **0.14/minute ireland 1890 924 204 israel 972-3-9288-504/544 italy 39 02 92 60 8484 netherlands 31 (0) 20 547 2111 spain 34 (91) 631 3300 sweden 0200-88 22 55 switzerland 0800 80 53 53 united kingdom 44 (0) 118 9276201 other european countries: www.agilent.com/? nd/contactus revised: july 17, 2008 product speci? cations and descriptions in this document subject to change without notice. ? agilent technologies, inc. 2003, 2004, 2008 printed in usa, december 4, 2008 5968-9188e remove all doubt our repair and calibration services will get your equipment back to you, performing like new, when prom- ised. you will get full value out of your agilent equipment through- out its lifetime. your equipment will be serviced by agilent-trained technicians using the latest factory calibration procedures, automated repair diagnostics and genuine parts. you will always have the utmost con? dence in your measurements. agilent offers a wide range of ad- ditional expert test and measure- ment services for your equipment, including initial start-up assistance, onsite education and training, as well as design, system integration, and project management. for more information on repair and calibration services, go to: www.agilent.com/? nd/open agilent open simpli? es the process of connecting and programming test systems to help engineers design, validate and manufacture electronic products. agilent offers open connectivity for a broad range of system-ready instruments, open industry software, pc-standard i/o and global support, which are combined to more easily integrate test system development. www.lxistandard.org lxi is the lan-based successor to gpib, providing faster, more ef? cient connectivity. agilent is a founding member of the lxi consortium. www.agilent.com/? nd/removealldoubt microsoft is a u.s. registered trademark of microsoft corporation. mipi? word marks and logos are trademarks owned by the mipi alliance, inc. and any use of such marks by agilent is under license. other trademarks and trade names are those of their respective owners.

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